Simulation Results: rom_ctrl/64kb

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.77 %
  • code
  • 99.46 %
  • assert
  • 96.95 %
  • func
  • 96.90 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.22 %
  • toggle
  • 99.87 %
  • FSM
  • 100.00 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rom_ctrl_smoke 7.220s 736.188us 1 1 100.00
rom_ctrl_stress_all 23.350s 833.634us 1 1 100.00
rom_ctrl_max_throughput_chk 7.360s 217.851us 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 166.520s 4321.987us 1 1 100.00
rom_ctrl_kmac_err_chk 12.450s 752.160us 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 112.140s 11347.211us 1 1 100.00
rom_ctrl_sec_cm 484.640s 4525.483us 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.140s 1558.326us 1 1 100.00
rom_ctrl_tl_errors 8.720s 699.075us 1 1 100.00
rom_ctrl_tl_intg_err 51.390s 282.589us 1 1 100.00
rom_ctrl_alert_test 6.170s 214.329us 1 1 100.00
rom_ctrl_mem_walk 6.530s 545.332us 1 1 100.00
rom_ctrl_mem_partial_access 5.820s 369.990us 1 1 100.00
rom_ctrl_csr_hw_reset 10.040s 710.009us 1 1 100.00
rom_ctrl_csr_rw 5.490s 1306.461us 1 1 100.00
rom_ctrl_csr_bit_bash 5.910s 727.141us 1 1 100.00
rom_ctrl_csr_aliasing 7.060s 1687.920us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.490s 1160.308us 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.410s 2517.332us 1 1 100.00