Simulation Results: rstmgr

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.02 %
  • code
  • 99.03 %
  • assert
  • 98.26 %
  • func
  • 96.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 97.71 %
  • toggle
  • 99.08 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rstmgr_smoke 1.140s 126.034us 1 1 100.00
rstmgr_por_stretcher 0.880s 164.334us 1 1 100.00
rstmgr_reset 5.610s 2081.375us 1 1 100.00
rstmgr_sw_rst_reset_race 1.240s 167.319us 1 1 100.00
rstmgr_sw_rst 2.010s 473.943us 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.330s 187.622us 1 1 100.00
rstmgr_leaf_rst_cnsty 4.090s 1276.835us 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.020s 301.816us 1 1 100.00
rstmgr_stress_all 10.510s 4797.486us 1 1 100.00
rstmgr_sec_cm 10.010s 8519.894us 1 1 100.00
rstmgr_tl_errors 1.400s 209.732us 1 1 100.00
rstmgr_tl_intg_err 1.970s 498.124us 1 1 100.00
rstmgr_alert_test 0.820s 57.573us 1 1 100.00
rstmgr_csr_hw_reset 0.780s 107.958us 1 1 100.00
rstmgr_csr_rw 0.780s 74.497us 1 1 100.00
rstmgr_csr_bit_bash 8.850s 2642.755us 1 1 100.00
rstmgr_csr_aliasing 1.580s 152.528us 1 1 100.00
rstmgr_same_csr_outstanding 0.860s 85.488us 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.050s 124.404us 1 1 100.00