Simulation Results: spi_host

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.33 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 87.82 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 26 26 100.00
spi_host_smoke 30.000s 3542.638us 1 1 100.00
spi_host_speed 2.000s 93.758us 1 1 100.00
spi_host_upper_range_clkdiv 462.000s 15833.586us 1 1 100.00
spi_host_performance 1.000s 63.620us 1 1 100.00
spi_host_sw_reset 5.000s 253.281us 1 1 100.00
spi_host_overflow_underflow 2.000s 89.445us 1 1 100.00
spi_host_error_cmd 1.000s 15.043us 1 1 100.00
spi_host_event 19.000s 2908.945us 1 1 100.00
spi_host_passthrough_mode 1.000s 39.640us 1 1 100.00
spi_host_status_stall 392.000s 87988.292us 1 1 100.00
spi_host_idlecsbactive 4.000s 168.913us 1 1 100.00
spi_host_stress_all 3.000s 588.017us 1 1 100.00
spi_host_spien 3.000s 656.161us 1 1 100.00
spi_host_tl_errors 1.000s 174.496us 1 1 100.00
spi_host_tl_intg_err 2.000s 395.318us 1 1 100.00
spi_host_sec_cm 1.000s 162.984us 1 1 100.00
spi_host_intr_test 1.000s 18.702us 1 1 100.00
spi_host_alert_test 2.000s 23.634us 1 1 100.00
spi_host_mem_walk 1.000s 16.055us 1 1 100.00
spi_host_mem_partial_access 1.000s 32.042us 1 1 100.00
spi_host_csr_hw_reset 1.000s 64.948us 1 1 100.00
spi_host_csr_rw 2.000s 18.710us 1 1 100.00
spi_host_csr_bit_bash 2.000s 41.991us 1 1 100.00
spi_host_csr_aliasing 1.000s 38.331us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 19.536us 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 54.124us 1 1 100.00