Simulation Results

unmapped

31/31 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				31	31	100.00
	sram_ctrl_smoke	5.000s	1375.837us	1	1	100.00
	sram_ctrl_multiple_keys	22.000s	4495.236us	1	1	100.00
	sram_ctrl_bijection	141.000s	14179.476us	1	1	100.00
	sram_ctrl_stress_pipeline	72.000s	2349.705us	1	1	100.00
	sram_ctrl_partial_access	2.000s	354.581us	1	1	100.00
	sram_ctrl_partial_access_b2b	303.000s	25232.452us	1	1	100.00
	sram_ctrl_max_throughput	4.000s	740.852us	1	1	100.00
	sram_ctrl_throughput_w_partial_write	5.000s	1392.404us	1	1	100.00
	sram_ctrl_throughput_w_readback	5.000s	6711.960us	1	1	100.00
	sram_ctrl_lc_escalation	27.000s	31512.113us	1	1	100.00
	sram_ctrl_access_during_key_req	49.000s	11424.035us	1	1	100.00
	sram_ctrl_executable	6.000s	1037.983us	1	1	100.00
	sram_ctrl_regwen	10.000s	15092.669us	1	1	100.00
	sram_ctrl_ram_cfg	4.000s	343.176us	1	1	100.00
	sram_ctrl_mem_walk	231.000s	98298.335us	1	1	100.00
	sram_ctrl_mem_partial_access	53.000s	4283.995us	1	1	100.00
	sram_ctrl_readback_err	5.000s	5581.755us	1	1	100.00
	sram_ctrl_mubi_enc_err	5.000s	678.653us	1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	7.000s	1292.990us	1	1	100.00
	sram_ctrl_stress_all	216.000s	122458.246us	1	1	100.00
	sram_ctrl_sec_cm	4.000s	2641.529us	1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	14.000s	14174.516us	1	1	100.00
	sram_ctrl_tl_errors	4.000s	137.305us	1	1	100.00
	sram_ctrl_tl_intg_err	2.000s	521.266us	1	1	100.00
	sram_ctrl_alert_test	1.000s	39.091us	1	1	100.00
	sram_ctrl_csr_hw_reset	1.000s	25.960us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	22.286us	1	1	100.00
	sram_ctrl_csr_bit_bash	2.000s	28.105us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	68.832us	1	1	100.00
	sram_ctrl_same_csr_outstanding	2.000s	49.928us	1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	3.000s	366.709us	1	1	100.00

Simulation Results: sram_ctrl/main