Simulation Results

unmapped

31/31 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				31	31	100.00
	sram_ctrl_smoke	2.000s	57.939us	1	1	100.00
	sram_ctrl_multiple_keys	3.000s	774.522us	1	1	100.00
	sram_ctrl_bijection	6.000s	1830.138us	1	1	100.00
	sram_ctrl_stress_pipeline	147.000s	16380.452us	1	1	100.00
	sram_ctrl_partial_access	2.000s	110.246us	1	1	100.00
	sram_ctrl_partial_access_b2b	136.000s	39861.247us	1	1	100.00
	sram_ctrl_max_throughput	2.000s	503.066us	1	1	100.00
	sram_ctrl_throughput_w_partial_write	1.000s	46.560us	1	1	100.00
	sram_ctrl_throughput_w_readback	2.000s	194.186us	1	1	100.00
	sram_ctrl_lc_escalation	7.000s	2559.731us	1	1	100.00
	sram_ctrl_access_during_key_req	11.000s	408.820us	1	1	100.00
	sram_ctrl_executable	3.000s	188.906us	1	1	100.00
	sram_ctrl_regwen	7.000s	1413.324us	1	1	100.00
	sram_ctrl_ram_cfg	2.000s	88.596us	1	1	100.00
	sram_ctrl_mem_walk	5.000s	393.613us	1	1	100.00
	sram_ctrl_mem_partial_access	3.000s	49.358us	1	1	100.00
	sram_ctrl_readback_err	1.000s	37.306us	1	1	100.00
	sram_ctrl_mubi_enc_err	2.000s	138.115us	1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	25.000s	1530.017us	1	1	100.00
	sram_ctrl_stress_all	18.000s	3072.152us	1	1	100.00
	sram_ctrl_sec_cm	3.000s	1216.753us	1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.000s	992.824us	1	1	100.00
	sram_ctrl_tl_errors	3.000s	45.263us	1	1	100.00
	sram_ctrl_tl_intg_err	2.000s	764.459us	1	1	100.00
	sram_ctrl_alert_test	1.000s	33.009us	1	1	100.00
	sram_ctrl_csr_hw_reset	1.000s	19.119us	1	1	100.00
	sram_ctrl_csr_rw	2.000s	11.477us	1	1	100.00
	sram_ctrl_csr_bit_bash	3.000s	203.946us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	33.627us	1	1	100.00
	sram_ctrl_same_csr_outstanding	1.000s	22.383us	1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	1.000s	35.146us	1	1	100.00

Simulation Results: sram_ctrl/ret