Simulation Results: sysrst_ctrl

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.21 %
  • code
  • 93.80 %
  • assert
  • 95.31 %
  • func
  • 60.53 %
  • line
  • 97.82 %
  • branch
  • 97.78 %
  • cond
  • 95.18 %
  • toggle
  • 100.00 %
  • FSM
  • 78.21 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 27 27 100.00
sysrst_ctrl_smoke 3.160s 2121.749us 1 1 100.00
sysrst_ctrl_in_out_inverted 5.390s 2461.390us 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.690s 2211.017us 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.890s 2562.632us 1 1 100.00
sysrst_ctrl_pin_access_test 4.240s 2074.630us 1 1 100.00
sysrst_ctrl_pin_override_test 3.200s 2511.782us 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 6.470s 2610.099us 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.180s 2813.981us 1 1 100.00
sysrst_ctrl_auto_blk_key_output 5.220s 3372.581us 1 1 100.00
sysrst_ctrl_ultra_low_pwr 5.750s 8035.148us 1 1 100.00
sysrst_ctrl_combo_detect 93.020s 95073.671us 1 1 100.00
sysrst_ctrl_edge_detect 5.490s 2433.368us 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 42.300s 22836.198us 1 1 100.00
sysrst_ctrl_feature_disable 69.990s 34763.089us 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 16.240s 7937.953us 1 1 100.00
sysrst_ctrl_stress_all 3.780s 6067.673us 1 1 100.00
sysrst_ctrl_sec_cm 73.810s 42013.353us 1 1 100.00
sysrst_ctrl_tl_errors 2.040s 2172.833us 1 1 100.00
sysrst_ctrl_tl_intg_err 11.670s 22461.402us 1 1 100.00
sysrst_ctrl_alert_test 1.900s 2040.632us 1 1 100.00
sysrst_ctrl_intr_test 3.180s 2017.097us 1 1 100.00
sysrst_ctrl_csr_hw_reset 4.680s 4031.442us 1 1 100.00
sysrst_ctrl_csr_rw 1.550s 2057.108us 1 1 100.00
sysrst_ctrl_csr_bit_bash 107.410s 39078.647us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.460s 3186.779us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.850s 4572.458us 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 3.170s 2117.132us 1 1 100.00