Simulation Results: adc_ctrl

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.76 %
  • code
  • 94.83 %
  • assert
  • 92.54 %
  • func
  • 12.92 %
  • line
  • 98.74 %
  • branch
  • 97.22 %
  • cond
  • 86.52 %
  • toggle
  • 99.76 %
  • FSM
  • 91.89 %
Validation stages
unmapped
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 15 25 60.00
adc_ctrl_smoke 2.240s 5709.460us 1 1 100.00
adc_ctrl_filters_polled 0.820s 498.703us 0 1 0.00
adc_ctrl_filters_polled_fixed 1.050s 527.407us 0 1 0.00
adc_ctrl_filters_interrupt 1.090s 320.710us 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.130s 374.413us 0 1 0.00
adc_ctrl_filters_wakeup 1.480s 489.311us 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.780s 345.537us 0 1 0.00
adc_ctrl_clock_gating 0.970s 440.152us 0 1 0.00
adc_ctrl_filters_both 0.710s 406.546us 0 1 0.00
adc_ctrl_poweron_counter 1.670s 3533.548us 1 1 100.00
adc_ctrl_lowpower_counter 50.120s 29758.624us 1 1 100.00
adc_ctrl_fsm_reset 36.110s 69963.497us 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 0.990s 692.479us 0 1 0.00
adc_ctrl_stress_all 11.580s 6674.343us 0 1 0.00
adc_ctrl_sec_cm 7.090s 7415.460us 1 1 100.00
adc_ctrl_tl_errors 1.860s 443.854us 1 1 100.00
adc_ctrl_tl_intg_err 5.330s 4401.502us 1 1 100.00
adc_ctrl_intr_test 1.160s 400.329us 1 1 100.00
adc_ctrl_alert_test 1.000s 368.806us 1 1 100.00
adc_ctrl_csr_hw_reset 2.150s 807.663us 1 1 100.00
adc_ctrl_csr_rw 1.180s 432.196us 1 1 100.00
adc_ctrl_csr_bit_bash 46.520s 27260.502us 1 1 100.00
adc_ctrl_csr_aliasing 4.010s 988.442us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.560s 2320.883us 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.230s 440.949us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 30257216116060791777104304314917415072350010746124856951983386264805192474542 388
UVM_INFO @ 498702889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 58186916650867624287052406693324954275246440789740071982967873002564719943301 388
UVM_INFO @ 527406787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 22789890384281298553930720908075406863706826614547111212122301617953896696846 388
UVM_INFO @ 320709735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 39706017615351442256441960398537610628176034499088500270647823260832021616276 388
UVM_INFO @ 374412716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 109877852172791232870927571268860931639946064995659228974445296855692428283310 388
UVM_INFO @ 489310623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 113470221891570151632826395607052514035674980982630787830053316091449079245040 388
UVM_INFO @ 345537078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 104973213537710243024233411607140668124356771390198706082397211324370335329554 388
UVM_INFO @ 440152436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 93368847161848237154877250640479342075771728482089383426119443774110880831294 388
UVM_INFO @ 406545747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 60570936984174820337410018798878455272708800283611548551237380046112915468672 394
UVM_INFO @ 692478877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 106271228744417880245635763945568292888417155703361248938477440585686828303256 391
UVM_INFO @ 6674342945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---