Simulation Results: csrng

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.59 %
  • code
  • 92.32 %
  • assert
  • 94.32 %
  • func
  • 64.13 %
  • block
  • 97.02 %
  • line
  • 97.73 %
  • branch
  • 92.60 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
unmapped
84.21%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 16 19 84.21
csrng_smoke 2.000s 27.295us 1 1 100.00
csrng_cmds 5.000s 80.748us 0 1 0.00
csrng_stress_all 178.000s 13119.355us 1 1 100.00
csrng_intr 6.000s 569.514us 1 1 100.00
csrng_alert 7.000s 345.410us 1 1 100.00
csrng_err 1.000s 33.211us 1 1 100.00
csrng_regwen 2.000s 5.719us 0 1 0.00
csrng_stress_all_with_rand_reset 10802.050s 0.000us 0 1 0.00
csrng_sec_cm 7.000s 196.265us 1 1 100.00
csrng_tl_errors 5.000s 317.101us 1 1 100.00
csrng_tl_intg_err 4.000s 156.169us 1 1 100.00
csrng_alert_test 1.000s 17.254us 1 1 100.00
csrng_intr_test 1.000s 44.108us 1 1 100.00
csrng_csr_hw_reset 2.000s 58.630us 1 1 100.00
csrng_csr_rw 1.000s 15.093us 1 1 100.00
csrng_csr_bit_bash 6.000s 137.389us 1 1 100.00
csrng_csr_aliasing 3.000s 44.922us 1 1 100.00
csrng_same_csr_outstanding 4.000s 215.644us 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 21.345us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 112454343639011429164491536586009614559989470276820052437235612279404368337550 100
UVM_INFO @ 80748230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 4117794054979963097284566741791508477061708114275114483722333747093864561086 99
UVM_INFO @ 5719328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 408121361014534959867462262279468815608741734602550822861148728354233719574 None