Simulation Results: edn/edn1

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.45 %
  • code
  • 82.40 %
  • assert
  • 98.44 %
  • func
  • 81.51 %
  • line
  • 98.10 %
  • branch
  • 93.29 %
  • cond
  • 89.62 %
  • toggle
  • 85.56 %
  • FSM
  • 45.45 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 21 21 100.00
edn_smoke 0.840s 75.825us 1 1 100.00
edn_regwen 0.990s 51.693us 1 1 100.00
edn_genbits 0.820s 65.659us 1 1 100.00
edn_stress_all 1.620s 405.062us 1 1 100.00
edn_stress_all_with_rand_reset 41.120s 5378.286us 1 1 100.00
edn_intr 0.810s 26.236us 1 1 100.00
edn_alert 1.020s 29.918us 1 1 100.00
edn_err 0.950s 56.858us 1 1 100.00
edn_disable 0.840s 13.483us 1 1 100.00
edn_disable_auto_req_mode 0.850s 25.569us 1 1 100.00
edn_sec_cm 3.860s 351.384us 1 1 100.00
edn_tl_errors 1.940s 41.897us 1 1 100.00
edn_tl_intg_err 1.750s 319.676us 1 1 100.00
edn_alert_test 0.830s 17.220us 1 1 100.00
edn_intr_test 0.760s 16.605us 1 1 100.00
edn_csr_hw_reset 0.800s 33.494us 1 1 100.00
edn_csr_rw 0.760s 33.572us 1 1 100.00
edn_csr_bit_bash 1.470s 129.229us 1 1 100.00
edn_csr_aliasing 0.990s 97.201us 1 1 100.00
edn_same_csr_outstanding 1.040s 28.263us 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.900s 18.425us 1 1 100.00