Simulation Results: hmac

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.21 %
  • code
  • 97.96 %
  • assert
  • 97.80 %
  • func
  • 44.87 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 28 28 100.00
hmac_smoke 8.290s 871.838us 1 1 100.00
hmac_long_msg 59.750s 16612.001us 1 1 100.00
hmac_stress_reset 1.260s 47.254us 1 1 100.00
hmac_back_pressure 34.670s 4754.908us 1 1 100.00
hmac_datapath_stress 1.040s 92.685us 1 1 100.00
hmac_burst_wr 16.670s 1552.694us 1 1 100.00
hmac_error 86.050s 40134.106us 1 1 100.00
hmac_wipe_secret 80.890s 13111.433us 1 1 100.00
hmac_test_sha256_vectors 8.700s 746.861us 1 1 100.00
hmac_test_sha384_vectors 21.750s 992.752us 1 1 100.00
hmac_test_sha512_vectors 402.100s 14092.105us 1 1 100.00
hmac_test_hmac256_vectors 9.790s 332.773us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 1261.331us 1 1 100.00
hmac_test_hmac512_vectors 9.020s 3046.790us 1 1 100.00
hmac_stress_all 157.990s 3662.156us 1 1 100.00
hmac_stress_all_with_rand_reset 221.310s 4487.500us 1 1 100.00
hmac_directed 2.600s 1875.700us 1 1 100.00
hmac_sec_cm 0.840s 197.768us 1 1 100.00
hmac_tl_errors 2.910s 73.705us 1 1 100.00
hmac_tl_intg_err 1.570s 88.920us 1 1 100.00
hmac_intr_test 0.720s 14.653us 1 1 100.00
hmac_alert_test 0.760s 15.211us 1 1 100.00
hmac_csr_hw_reset 0.770s 42.548us 1 1 100.00
hmac_csr_rw 0.920s 48.623us 1 1 100.00
hmac_csr_bit_bash 8.850s 2486.238us 1 1 100.00
hmac_csr_aliasing 6.610s 1013.795us 1 1 100.00
hmac_same_csr_outstanding 1.410s 212.924us 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.240s 23.914us 1 1 100.00