Simulation Results: lc_ctrl/volatile_unlock_disabled

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.10 %
  • code
  • 83.43 %
  • assert
  • 94.69 %
  • func
  • 92.17 %
  • line
  • 97.19 %
  • branch
  • 93.70 %
  • cond
  • 79.31 %
  • toggle
  • 86.19 %
  • FSM
  • 60.75 %
Validation stages
unmapped
97.44%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 38 39 97.44
lc_ctrl_smoke 1.900s 241.400us 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.030s 42.133us 1 1 100.00
lc_ctrl_state_failure 9.170s 944.774us 1 1 100.00
lc_ctrl_state_post_trans 4.360s 308.785us 1 1 100.00
lc_ctrl_prog_failure 1.630s 107.508us 1 1 100.00
lc_ctrl_errors 6.980s 1744.230us 1 1 100.00
lc_ctrl_security_escalation 4.740s 535.069us 1 1 100.00
lc_ctrl_regwen_during_op 11.170s 250.094us 1 1 100.00
lc_ctrl_claim_transition_if 1.280s 22.021us 1 1 100.00
lc_ctrl_jtag_smoke 4.080s 817.394us 1 1 100.00
lc_ctrl_jtag_state_failure 21.310s 3372.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.880s 1012.499us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.510s 406.315us 1 1 100.00
lc_ctrl_jtag_errors 13.960s 5963.647us 1 1 100.00
lc_ctrl_jtag_access 4.040s 2542.788us 1 1 100.00
lc_ctrl_jtag_priority 2.040s 463.032us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.160s 1052.331us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.130s 404.423us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.010s 305.868us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.600s 1061.173us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.960s 1848.729us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.490s 79.464us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.670s 101.441us 1 1 100.00
lc_ctrl_jtag_alert_test 1.780s 61.301us 1 1 100.00
lc_ctrl_sec_mubi 6.490s 438.225us 1 1 100.00
lc_ctrl_sec_token_mux 6.510s 1795.759us 1 1 100.00
lc_ctrl_sec_token_digest 8.410s 594.988us 1 1 100.00
lc_ctrl_stress_all 78.880s 34019.546us 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 12.480s 4652.893us 0 1 0.00
lc_ctrl_sec_cm 7.320s 962.876us 1 1 100.00
lc_ctrl_tl_errors 3.880s 838.221us 1 1 100.00
lc_ctrl_tl_intg_err 1.440s 79.121us 1 1 100.00
lc_ctrl_alert_test 1.310s 29.451us 1 1 100.00
lc_ctrl_csr_hw_reset 1.020s 25.096us 1 1 100.00
lc_ctrl_csr_rw 0.810s 15.659us 1 1 100.00
lc_ctrl_csr_bit_bash 2.670s 109.863us 1 1 100.00
lc_ctrl_csr_aliasing 1.540s 76.819us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.650s 88.578us 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.560s 31.908us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 2718642763854676169495701273439860366516360114736358332672141156304533705050 6184
UVM_INFO @ 4652892560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---