Simulation Results: lc_ctrl/volatile_unlock_enabled

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.63 %
  • code
  • 84.15 %
  • assert
  • 94.69 %
  • func
  • 93.06 %
  • line
  • 97.13 %
  • branch
  • 93.37 %
  • cond
  • 79.22 %
  • toggle
  • 88.43 %
  • FSM
  • 62.62 %
Validation stages
unmapped
97.44%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 38 39 97.44
lc_ctrl_smoke 2.610s 51.711us 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.110s 16.505us 1 1 100.00
lc_ctrl_state_failure 8.690s 275.195us 1 1 100.00
lc_ctrl_state_post_trans 2.410s 73.596us 1 1 100.00
lc_ctrl_prog_failure 1.810s 61.004us 1 1 100.00
lc_ctrl_errors 4.760s 224.537us 1 1 100.00
lc_ctrl_security_escalation 6.160s 819.982us 1 1 100.00
lc_ctrl_regwen_during_op 8.080s 855.614us 1 1 100.00
lc_ctrl_claim_transition_if 0.990s 41.388us 1 1 100.00
lc_ctrl_jtag_smoke 6.370s 573.133us 1 1 100.00
lc_ctrl_jtag_state_failure 37.910s 1959.603us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.730s 450.290us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.380s 786.913us 1 1 100.00
lc_ctrl_jtag_errors 33.890s 3486.525us 1 1 100.00
lc_ctrl_jtag_access 7.210s 1343.549us 1 1 100.00
lc_ctrl_jtag_priority 3.020s 943.452us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.880s 544.659us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.320s 366.595us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.820s 370.248us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 15.890s 1865.351us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.500s 2143.951us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.530s 170.028us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.300s 396.583us 1 1 100.00
lc_ctrl_jtag_alert_test 1.080s 282.941us 1 1 100.00
lc_ctrl_sec_mubi 5.220s 1242.521us 1 1 100.00
lc_ctrl_sec_token_mux 5.680s 893.568us 1 1 100.00
lc_ctrl_sec_token_digest 6.870s 289.956us 1 1 100.00
lc_ctrl_stress_all 108.110s 11546.069us 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 1.790s 105.127us 0 1 0.00
lc_ctrl_sec_cm 6.750s 272.074us 1 1 100.00
lc_ctrl_tl_errors 1.910s 325.039us 1 1 100.00
lc_ctrl_tl_intg_err 2.060s 118.683us 1 1 100.00
lc_ctrl_alert_test 1.110s 41.768us 1 1 100.00
lc_ctrl_csr_hw_reset 0.840s 22.895us 1 1 100.00
lc_ctrl_csr_rw 0.810s 57.824us 1 1 100.00
lc_ctrl_csr_bit_bash 2.740s 208.683us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 26.255us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.410s 173.453us 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.540s 91.257us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 73991170786880474144398608724499355766790629874106647539695473256073027622018 150
UVM_INFO @ 105126681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---