Simulation Results: otbn

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.45 %
  • code
  • 93.97 %
  • assert
  • 90.22 %
  • func
  • 99.15 %
  • block
  • 99.31 %
  • line
  • 99.48 %
  • branch
  • 91.51 %
  • toggle
  • 87.34 %
  • FSM
  • 97.56 %
Validation stages
unmapped
90.48%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 38 42 90.48
otbn_smoke 9.000s 45.479us 1 1 100.00
otbn_smoke_vectorized 6.000s 61.585us 1 1 100.00
otbn_single 7.000s 51.110us 1 1 100.00
otbn_multi 80.000s 753.354us 1 1 100.00
otbn_reset 31.000s 164.343us 1 1 100.00
otbn_multi_err 10.000s 52.946us 0 1 0.00
otbn_imem_err 11.000s 35.410us 1 1 100.00
otbn_dmem_err 33.000s 72.423us 1 1 100.00
otbn_escalate 33.000s 92.992us 1 1 100.00
otbn_alu_bignum_mod_err 32.000s 220.395us 1 1 100.00
otbn_controller_ispr_rdata_err 32.000s 195.162us 0 1 0.00
otbn_mac_bignum_acc_err 8.000s 738.759us 1 1 100.00
otbn_rf_bignum_intg_err 6.000s 547.882us 1 1 100.00
otbn_rf_base_intg_err 7.000s 33.810us 1 1 100.00
otbn_stress_all 41.000s 159.752us 1 1 100.00
otbn_stress_all_with_rand_reset 79.000s 463.035us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 115.010us 0 1 0.00
otbn_illegal_mem_acc 17.000s 34.551us 1 1 100.00
otbn_sw_errs_fatal_chk 14.000s 213.065us 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 13.727us 1 1 100.00
otbn_rnd_sec_cm 24.000s 167.513us 1 1 100.00
otbn_ctrl_redun 34.000s 30.629us 1 1 100.00
otbn_sec_wipe_err 9.000s 54.720us 1 1 100.00
otbn_urnd_err 9.000s 31.774us 1 1 100.00
otbn_sw_no_acc 8.000s 31.467us 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 31.431us 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 29.027us 1 1 100.00
otbn_partial_wipe 5.000s 120.679us 1 1 100.00
otbn_passthru_mem_tl_intg_err 44.000s 210.415us 1 1 100.00
otbn_sec_cm 303.000s 3317.622us 1 1 100.00
otbn_tl_errors 5.000s 136.195us 1 1 100.00
otbn_tl_intg_err 18.000s 568.465us 1 1 100.00
otbn_intr_test 4.000s 56.747us 1 1 100.00
otbn_alert_test 29.000s 121.010us 1 1 100.00
otbn_mem_walk 49.000s 7103.238us 1 1 100.00
otbn_mem_partial_access 25.000s 575.556us 1 1 100.00
otbn_csr_hw_reset 29.000s 15.606us 1 1 100.00
otbn_csr_rw 28.000s 25.690us 1 1 100.00
otbn_csr_bit_bash 31.000s 41.678us 1 1 100.00
otbn_csr_aliasing 28.000s 17.467us 1 1 100.00
otbn_same_csr_outstanding 4.000s 92.217us 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 31.000s 62.658us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 57669781952816163706050505857485177898142253677043748083927329735405117418838 211
UVM_INFO @ 52946162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_controller_ispr_rdata_err 63685386777118390351228124346810131376813171159163519396260582793846048981283 110
UVM_INFO @ 195161681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 68542815592443516588791266272739959183845656301318183250374893467023205490631 170
UVM_INFO @ 463034532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_zero_state_err_urnd 80775449377381210899267387093564655598887563347533349025194274932793579431743 107
UVM_ERROR @ 115010302 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 115010302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---