| unmapped |
|
93.33% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 28 | 30 | 93.33 | |||
| otp_ctrl_wake_up | 1.420s | 92.140us | 1 | 1 | 100.00 | |
| otp_ctrl_smoke | 6.920s | 2455.914us | 1 | 1 | 100.00 | |
| otp_ctrl_partition_walk | 13.050s | 1396.143us | 1 | 1 | 100.00 | |
| otp_ctrl_low_freq_read | 8.790s | 3132.647us | 1 | 1 | 100.00 | |
| otp_ctrl_init_fail | 2.630s | 109.104us | 1 | 1 | 100.00 | |
| otp_ctrl_background_chks | 15.360s | 2569.759us | 1 | 1 | 100.00 | |
| otp_ctrl_parallel_lc_req | 7.300s | 836.759us | 1 | 1 | 100.00 | |
| otp_ctrl_parallel_lc_esc | 22.170s | 2385.211us | 1 | 1 | 100.00 | |
| otp_ctrl_dai_lock | 5.450s | 316.857us | 1 | 1 | 100.00 | |
| otp_ctrl_dai_errs | 15.420s | 707.981us | 1 | 1 | 100.00 | |
| otp_ctrl_check_fail | 21.640s | 923.444us | 1 | 1 | 100.00 | |
| otp_ctrl_macro_errs | 12.430s | 1104.565us | 0 | 1 | 0.00 | |
| otp_ctrl_parallel_key_req | 9.300s | 1096.093us | 1 | 1 | 100.00 | |
| otp_ctrl_regwen | 3.770s | 440.996us | 1 | 1 | 100.00 | |
| otp_ctrl_test_access | 23.390s | 2678.448us | 1 | 1 | 100.00 | |
| otp_ctrl_stress_all_with_rand_reset | 31.070s | 3235.984us | 0 | 1 | 0.00 | |
| otp_ctrl_stress_all | 82.010s | 47121.410us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 177.550s | 155382.309us | 1 | 1 | 100.00 | |
| otp_ctrl_tl_errors | 3.610s | 291.361us | 1 | 1 | 100.00 | |
| otp_ctrl_tl_intg_err | 13.950s | 2398.201us | 1 | 1 | 100.00 | |
| otp_ctrl_alert_test | 2.830s | 513.733us | 1 | 1 | 100.00 | |
| otp_ctrl_intr_test | 1.550s | 599.747us | 1 | 1 | 100.00 | |
| otp_ctrl_mem_walk | 1.530s | 56.015us | 1 | 1 | 100.00 | |
| otp_ctrl_mem_partial_access | 1.320s | 148.392us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_hw_reset | 2.030s | 1002.787us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_rw | 1.720s | 597.198us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_bit_bash | 3.220s | 1288.507us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 3.240s | 121.742us | 1 | 1 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 2.760s | 75.425us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_mem_rw_with_rand_reset | 2.260s | 146.618us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* | 1 test run | |||
| otp_ctrl_macro_errs | 56784040638042889016849389542542677926597031849799789797280240515709513908568 | 6177 |
UVM_INFO @ 1104565083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state | 1 test run | |||
| otp_ctrl_stress_all_with_rand_reset | 73627667894978163968560246903057519813377276427457585855441083287037183354423 | 11502 |
UVM_INFO @ 3235984289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|