Simulation Results: rom_ctrl/32kb

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.02 %
  • code
  • 99.48 %
  • assert
  • 97.67 %
  • func
  • 96.90 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.37 %
  • toggle
  • 99.80 %
  • FSM
  • 100.00 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rom_ctrl_smoke 4.410s 421.297us 1 1 100.00
rom_ctrl_stress_all 9.680s 3032.324us 1 1 100.00
rom_ctrl_max_throughput_chk 4.630s 739.004us 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.900s 10512.029us 1 1 100.00
rom_ctrl_kmac_err_chk 7.770s 638.594us 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 147.880s 4092.330us 1 1 100.00
rom_ctrl_sec_cm 211.120s 472.518us 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.820s 4121.453us 1 1 100.00
rom_ctrl_tl_errors 8.780s 779.662us 1 1 100.00
rom_ctrl_tl_intg_err 25.200s 257.121us 1 1 100.00
rom_ctrl_alert_test 3.510s 385.340us 1 1 100.00
rom_ctrl_mem_walk 3.400s 220.494us 1 1 100.00
rom_ctrl_mem_partial_access 3.650s 125.699us 1 1 100.00
rom_ctrl_csr_hw_reset 5.630s 831.868us 1 1 100.00
rom_ctrl_csr_rw 4.730s 170.213us 1 1 100.00
rom_ctrl_csr_bit_bash 4.040s 216.608us 1 1 100.00
rom_ctrl_csr_aliasing 3.160s 372.361us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.950s 1143.443us 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.110s 276.626us 1 1 100.00