Simulation Results: rom_ctrl/64kb

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.90 %
  • code
  • 99.25 %
  • assert
  • 97.09 %
  • func
  • 97.37 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 97.47 %
  • toggle
  • 99.90 %
  • FSM
  • 100.00 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rom_ctrl_smoke 7.390s 225.160us 1 1 100.00
rom_ctrl_stress_all 24.270s 828.961us 1 1 100.00
rom_ctrl_max_throughput_chk 7.550s 1151.200us 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.290s 2973.312us 1 1 100.00
rom_ctrl_kmac_err_chk 13.520s 387.228us 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 333.110s 4822.330us 1 1 100.00
rom_ctrl_sec_cm 469.030s 2458.882us 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.330s 2244.844us 1 1 100.00
rom_ctrl_tl_errors 11.120s 208.917us 1 1 100.00
rom_ctrl_tl_intg_err 55.550s 1283.159us 1 1 100.00
rom_ctrl_alert_test 5.970s 789.977us 1 1 100.00
rom_ctrl_mem_walk 6.230s 205.359us 1 1 100.00
rom_ctrl_mem_partial_access 7.340s 1165.437us 1 1 100.00
rom_ctrl_csr_hw_reset 12.980s 967.842us 1 1 100.00
rom_ctrl_csr_rw 10.180s 4128.135us 1 1 100.00
rom_ctrl_csr_bit_bash 6.860s 923.650us 1 1 100.00
rom_ctrl_csr_aliasing 7.960s 294.913us 1 1 100.00
rom_ctrl_same_csr_outstanding 11.500s 8233.234us 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.860s 225.937us 1 1 100.00