Simulation Results: rstmgr

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.57 %
  • code
  • 99.32 %
  • assert
  • 98.39 %
  • func
  • 98.01 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.68 %
  • toggle
  • 99.25 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rstmgr_smoke 1.770s 288.366us 1 1 100.00
rstmgr_por_stretcher 1.080s 183.663us 1 1 100.00
rstmgr_reset 3.570s 1007.294us 1 1 100.00
rstmgr_sw_rst_reset_race 1.310s 128.492us 1 1 100.00
rstmgr_sw_rst 2.060s 457.116us 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.360s 201.739us 1 1 100.00
rstmgr_leaf_rst_cnsty 8.080s 2436.999us 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.080s 302.111us 1 1 100.00
rstmgr_stress_all 25.980s 10817.325us 1 1 100.00
rstmgr_sec_cm 11.050s 8436.057us 1 1 100.00
rstmgr_tl_errors 1.480s 121.454us 1 1 100.00
rstmgr_tl_intg_err 2.750s 801.787us 1 1 100.00
rstmgr_alert_test 1.280s 171.120us 1 1 100.00
rstmgr_csr_hw_reset 0.970s 129.705us 1 1 100.00
rstmgr_csr_rw 0.830s 86.707us 1 1 100.00
rstmgr_csr_bit_bash 7.890s 2238.382us 1 1 100.00
rstmgr_csr_aliasing 3.150s 439.913us 1 1 100.00
rstmgr_same_csr_outstanding 1.210s 156.082us 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.030s 120.284us 1 1 100.00