Simulation Results: rv_timer

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.98 %
  • code
  • 99.54 %
  • assert
  • 96.82 %
  • func
  • 85.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 98.15 %
  • toggle
  • 100.00 %
Validation stages
unmapped
78.95%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 15 19 78.95
rv_timer_random 1.380s 903.862us 1 1 100.00
rv_timer_min 3.440s 2543.876us 0 1 0.00
rv_timer_max 0.690s 53.661us 0 1 0.00
rv_timer_disabled 1.090s 564.561us 1 1 100.00
rv_timer_cfg_update_on_fly 169.590s 284035.802us 1 1 100.00
rv_timer_random_reset 0.640s 71.725us 0 1 0.00
rv_timer_stress_all_with_rand_reset 13.230s 2368.345us 0 1 0.00
rv_timer_stress_all 3.050s 2352.189us 1 1 100.00
rv_timer_sec_cm 1.010s 103.502us 1 1 100.00
rv_timer_tl_errors 1.170s 33.293us 1 1 100.00
rv_timer_tl_intg_err 0.800s 86.428us 1 1 100.00
rv_timer_intr_test 0.660s 37.556us 1 1 100.00
rv_timer_alert_test 0.670s 11.097us 1 1 100.00
rv_timer_csr_hw_reset 0.680s 31.201us 1 1 100.00
rv_timer_csr_rw 0.590s 27.126us 1 1 100.00
rv_timer_csr_bit_bash 1.260s 41.619us 1 1 100.00
rv_timer_csr_aliasing 0.780s 84.887us 1 1 100.00
rv_timer_same_csr_outstanding 0.780s 16.277us 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.750s 17.977us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 80267011217078754165022416400740848200959475484915290739587168271322046604801 78
UVM_INFO @ 2543875517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 31451881475676206789833892111476375041811130597044798215103519604271086023969 75
UVM_INFO @ 71725080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 85979806191745578724243910389562059141800576180888490060763770716483728148824 75
UVM_INFO @ 53660841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
rv_timer_stress_all_with_rand_reset 40184382239456135405698185707133221698222581573122592490819067498772996038312 220
UVM_INFO @ 2368345251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---