Simulation Results: spi_host

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.06 %
  • code
  • 95.03 %
  • assert
  • 95.08 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 26 26 100.00
spi_host_smoke 16.000s 1532.884us 1 1 100.00
spi_host_speed 1.000s 355.919us 1 1 100.00
spi_host_upper_range_clkdiv 131.000s 19533.944us 1 1 100.00
spi_host_performance 1.000s 24.818us 1 1 100.00
spi_host_sw_reset 2.000s 79.368us 1 1 100.00
spi_host_overflow_underflow 3.000s 165.843us 1 1 100.00
spi_host_error_cmd 1.000s 27.582us 1 1 100.00
spi_host_event 3.000s 1256.755us 1 1 100.00
spi_host_passthrough_mode 1.000s 100.512us 1 1 100.00
spi_host_status_stall 32.000s 1697.859us 1 1 100.00
spi_host_idlecsbactive 2.000s 79.131us 1 1 100.00
spi_host_stress_all 6.000s 633.128us 1 1 100.00
spi_host_spien 12.000s 5155.602us 1 1 100.00
spi_host_tl_errors 3.000s 485.696us 1 1 100.00
spi_host_tl_intg_err 2.000s 855.223us 1 1 100.00
spi_host_sec_cm 1.000s 133.653us 1 1 100.00
spi_host_intr_test 1.000s 49.175us 1 1 100.00
spi_host_alert_test 1.000s 18.743us 1 1 100.00
spi_host_mem_walk 1.000s 26.476us 1 1 100.00
spi_host_mem_partial_access 2.000s 69.183us 1 1 100.00
spi_host_csr_hw_reset 1.000s 43.436us 1 1 100.00
spi_host_csr_rw 1.000s 20.792us 1 1 100.00
spi_host_csr_bit_bash 2.000s 234.578us 1 1 100.00
spi_host_csr_aliasing 1.000s 32.029us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 29.085us 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 74.342us 1 1 100.00