Simulation Results

unmapped

31/31 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				31	31	100.00
	sram_ctrl_smoke	4.000s	583.830us	1	1	100.00
	sram_ctrl_multiple_keys	23.000s	4674.893us	1	1	100.00
	sram_ctrl_bijection	113.000s	2965.763us	1	1	100.00
	sram_ctrl_stress_pipeline	206.000s	21653.143us	1	1	100.00
	sram_ctrl_partial_access	3.000s	1432.072us	1	1	100.00
	sram_ctrl_partial_access_b2b	142.000s	41980.188us	1	1	100.00
	sram_ctrl_max_throughput	8.000s	4165.116us	1	1	100.00
	sram_ctrl_throughput_w_partial_write	4.000s	675.744us	1	1	100.00
	sram_ctrl_throughput_w_readback	5.000s	3735.811us	1	1	100.00
	sram_ctrl_lc_escalation	20.000s	4671.750us	1	1	100.00
	sram_ctrl_access_during_key_req	52.000s	74018.191us	1	1	100.00
	sram_ctrl_executable	31.000s	10902.857us	1	1	100.00
	sram_ctrl_regwen	6.000s	457.341us	1	1	100.00
	sram_ctrl_ram_cfg	4.000s	363.400us	1	1	100.00
	sram_ctrl_mem_walk	228.000s	84704.290us	1	1	100.00
	sram_ctrl_mem_partial_access	40.000s	963.348us	1	1	100.00
	sram_ctrl_readback_err	5.000s	671.869us	1	1	100.00
	sram_ctrl_mubi_enc_err	6.000s	696.572us	1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	16.000s	5146.130us	1	1	100.00
	sram_ctrl_stress_all	53.000s	40447.994us	1	1	100.00
	sram_ctrl_sec_cm	4.000s	1495.337us	1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	28.000s	39080.710us	1	1	100.00
	sram_ctrl_tl_errors	4.000s	257.969us	1	1	100.00
	sram_ctrl_tl_intg_err	4.000s	648.772us	1	1	100.00
	sram_ctrl_alert_test	2.000s	15.758us	1	1	100.00
	sram_ctrl_csr_hw_reset	2.000s	22.047us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	36.406us	1	1	100.00
	sram_ctrl_csr_bit_bash	1.000s	27.927us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	40.017us	1	1	100.00
	sram_ctrl_same_csr_outstanding	2.000s	19.080us	1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	4.000s	4397.601us	1	1	100.00

Simulation Results: sram_ctrl/main