Simulation Results

unmapped

31/31 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				31	31	100.00
	sram_ctrl_smoke	2.000s	60.822us	1	1	100.00
	sram_ctrl_multiple_keys	9.000s	1368.382us	1	1	100.00
	sram_ctrl_bijection	5.000s	456.245us	1	1	100.00
	sram_ctrl_stress_pipeline	134.000s	2849.767us	1	1	100.00
	sram_ctrl_partial_access	2.000s	170.637us	1	1	100.00
	sram_ctrl_partial_access_b2b	177.000s	4872.138us	1	1	100.00
	sram_ctrl_max_throughput	2.000s	35.768us	1	1	100.00
	sram_ctrl_throughput_w_partial_write	2.000s	39.653us	1	1	100.00
	sram_ctrl_throughput_w_readback	1.000s	186.190us	1	1	100.00
	sram_ctrl_lc_escalation	3.000s	120.932us	1	1	100.00
	sram_ctrl_access_during_key_req	9.000s	350.101us	1	1	100.00
	sram_ctrl_executable	3.000s	718.416us	1	1	100.00
	sram_ctrl_regwen	2.000s	72.908us	1	1	100.00
	sram_ctrl_ram_cfg	2.000s	82.578us	1	1	100.00
	sram_ctrl_mem_walk	7.000s	1523.899us	1	1	100.00
	sram_ctrl_mem_partial_access	5.000s	177.910us	1	1	100.00
	sram_ctrl_readback_err	1.000s	171.365us	1	1	100.00
	sram_ctrl_mubi_enc_err	2.000s	202.282us	1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	19.000s	894.009us	1	1	100.00
	sram_ctrl_stress_all	13.000s	543.953us	1	1	100.00
	sram_ctrl_sec_cm	4.000s	2610.550us	1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.000s	810.277us	1	1	100.00
	sram_ctrl_tl_errors	4.000s	295.555us	1	1	100.00
	sram_ctrl_tl_intg_err	2.000s	286.573us	1	1	100.00
	sram_ctrl_alert_test	2.000s	13.837us	1	1	100.00
	sram_ctrl_csr_hw_reset	2.000s	16.131us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	15.405us	1	1	100.00
	sram_ctrl_csr_bit_bash	2.000s	29.434us	1	1	100.00
	sram_ctrl_csr_aliasing	2.000s	29.704us	1	1	100.00
	sram_ctrl_same_csr_outstanding	1.000s	29.002us	1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	3.000s	37.755us	1	1	100.00

Simulation Results: sram_ctrl/ret