Simulation Results: sysrst_ctrl

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.47 %
  • code
  • 92.83 %
  • assert
  • 94.06 %
  • func
  • 69.52 %
  • line
  • 97.26 %
  • branch
  • 97.33 %
  • cond
  • 95.25 %
  • toggle
  • 99.32 %
  • FSM
  • 75.00 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 27 27 100.00
sysrst_ctrl_smoke 1.640s 2125.686us 1 1 100.00
sysrst_ctrl_in_out_inverted 3.090s 2465.478us 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.480s 2241.061us 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.250s 2544.064us 1 1 100.00
sysrst_ctrl_pin_access_test 3.340s 2217.608us 1 1 100.00
sysrst_ctrl_pin_override_test 4.680s 2510.825us 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.270s 2621.148us 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.420s 4272.368us 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.770s 4146.937us 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.830s 4450.721us 1 1 100.00
sysrst_ctrl_combo_detect 76.160s 145322.584us 1 1 100.00
sysrst_ctrl_edge_detect 5.740s 1028958.122us 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 35.380s 71217.791us 1 1 100.00
sysrst_ctrl_feature_disable 17.920s 35778.130us 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 4.810s 42028.307us 1 1 100.00
sysrst_ctrl_stress_all 15.620s 15348.584us 1 1 100.00
sysrst_ctrl_sec_cm 76.770s 42011.297us 1 1 100.00
sysrst_ctrl_tl_errors 3.260s 2614.068us 1 1 100.00
sysrst_ctrl_tl_intg_err 83.680s 42392.720us 1 1 100.00
sysrst_ctrl_alert_test 3.260s 2018.103us 1 1 100.00
sysrst_ctrl_intr_test 5.060s 2010.346us 1 1 100.00
sysrst_ctrl_csr_hw_reset 12.850s 6018.366us 1 1 100.00
sysrst_ctrl_csr_rw 1.790s 2070.351us 1 1 100.00
sysrst_ctrl_csr_bit_bash 13.190s 39190.207us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.660s 2580.944us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.710s 10550.834us 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.980s 2048.737us 1 1 100.00