Simulation Results: uart

 
28/05/2026 15:30:27 DVSim: v1.49.6 sha: 1d0cf80 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.26 %
  • code
  • 95.21 %
  • assert
  • 97.12 %
  • func
  • 42.46 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.93 %
  • toggle
  • 91.55 %
Validation stages
unmapped
92.59%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 25 27 92.59
uart_smoke 1.360s 525.485us 1 1 100.00
uart_tx_rx 13.180s 31241.931us 1 1 100.00
uart_fifo_full 22.560s 19750.758us 1 1 100.00
uart_fifo_overflow 19.050s 62879.817us 1 1 100.00
uart_fifo_reset 30.060s 87830.288us 1 1 100.00
uart_rx_oversample 32.040s 5426.476us 1 1 100.00
uart_intr 140.370s 288018.745us 1 1 100.00
uart_noise_filter 3.280s 5170.814us 0 1 0.00
uart_rx_start_bit_filter 42.210s 71990.057us 1 1 100.00
uart_rx_parity_err 17.330s 30815.388us 1 1 100.00
uart_tx_ovrd 9.140s 7617.367us 1 1 100.00
uart_loopback 14.920s 10831.204us 1 1 100.00
uart_perf 178.260s 4744.575us 1 1 100.00
uart_long_xfer_wo_dly 186.510s 184934.344us 1 1 100.00
uart_stress_all_with_rand_reset 26.330s 6169.360us 1 1 100.00
uart_stress_all 1.310s 1192.198us 0 1 0.00
uart_sec_cm 0.940s 164.594us 1 1 100.00
uart_tl_errors 1.390s 107.064us 1 1 100.00
uart_tl_intg_err 1.210s 328.947us 1 1 100.00
uart_intr_test 0.670s 12.221us 1 1 100.00
uart_alert_test 0.630s 52.814us 1 1 100.00
uart_csr_hw_reset 0.630s 14.495us 1 1 100.00
uart_csr_rw 0.800s 51.294us 1 1 100.00
uart_csr_bit_bash 2.010s 1136.250us 1 1 100.00
uart_csr_aliasing 0.950s 119.471us 1 1 100.00
uart_same_csr_outstanding 0.740s 25.466us 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.140s 29.918us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 2 test runs
uart_noise_filter 48878775503939346364950379674292192094912973272220721034259467595650625530853 75
UVM_ERROR @ 4115203186 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 4115235444 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (101 [0x65] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 4117880600 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 4117912858 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_stress_all 81641014733871146395155462226660617047136267900209437463191185354472697655217 76
UVM_ERROR @ 708058552 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 708078960 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (158 [0x9e] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 708099368 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 708119776 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (158 [0x9e] vs 247 [0xf7]) reg name: uart_reg_block.rdata