Simulation Results: adc_ctrl

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.16 %
  • code
  • 93.51 %
  • assert
  • 91.90 %
  • func
  • 13.07 %
  • line
  • 97.97 %
  • branch
  • 96.23 %
  • cond
  • 85.57 %
  • toggle
  • 98.58 %
  • FSM
  • 89.19 %
Validation stages
unmapped
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 15 25 60.00
adc_ctrl_smoke 9.250s 5836.238us 1 1 100.00
adc_ctrl_filters_polled 1.280s 459.117us 0 1 0.00
adc_ctrl_filters_polled_fixed 1.070s 337.524us 0 1 0.00
adc_ctrl_filters_interrupt 1.310s 468.842us 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.340s 341.872us 0 1 0.00
adc_ctrl_filters_wakeup 0.760s 436.062us 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.710s 399.733us 0 1 0.00
adc_ctrl_clock_gating 0.670s 462.483us 0 1 0.00
adc_ctrl_filters_both 1.310s 440.477us 0 1 0.00
adc_ctrl_poweron_counter 2.620s 2909.490us 1 1 100.00
adc_ctrl_lowpower_counter 4.150s 44636.038us 1 1 100.00
adc_ctrl_fsm_reset 34.010s 138568.396us 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 1.070s 1001.325us 0 1 0.00
adc_ctrl_stress_all 61.870s 143150.626us 0 1 0.00
adc_ctrl_sec_cm 11.150s 7790.102us 1 1 100.00
adc_ctrl_tl_errors 1.510s 443.221us 1 1 100.00
adc_ctrl_tl_intg_err 2.300s 4654.972us 1 1 100.00
adc_ctrl_intr_test 1.300s 440.634us 1 1 100.00
adc_ctrl_alert_test 1.080s 335.477us 1 1 100.00
adc_ctrl_csr_hw_reset 1.120s 1198.869us 1 1 100.00
adc_ctrl_csr_rw 0.830s 612.218us 1 1 100.00
adc_ctrl_csr_bit_bash 8.300s 27212.795us 1 1 100.00
adc_ctrl_csr_aliasing 2.740s 1268.444us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.440s 4552.777us 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.290s 382.183us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 30062275584641183886337267444342702154768358666984041383290802168192179013562 388
UVM_INFO @ 459117499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 86422520392104785395608520622576607032651979507907757305166508810696355688082 388
UVM_INFO @ 337523569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 89566104721823835439772033687798051089902397838676578573072829627132931980430 388
UVM_INFO @ 468842232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 67285168650746021085294363337237349548628255991159656886102956499266805459101 388
UVM_INFO @ 341872382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 34648401828137850471553537175247754728674686834367851148603018672590074180205 388
UVM_INFO @ 436061786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 100303892119316539468256911248411523893267492670006068724569625477018564965709 388
UVM_INFO @ 399732699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 16761464417878495394914582139438756628932486088024067778115512283799743500770 388
UVM_INFO @ 462482533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 37750670041836786002132949779337564623347435921465688041644400457005769245517 388
UVM_INFO @ 440477498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 39552801388824596979850270634359251306229113830094657986867732479585250228485 394
UVM_INFO @ 1001324728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 47483466204286338731640255725191290712389257846222589774082694622473210058284 513
UVM_INFO @ 143150626463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---