| Unmapped |
26 |
27 |
96.30 |
|
clkmgr_smoke |
1.150s |
191.950us |
1 |
1 |
100.00
|
|
clkmgr_extclk |
1.040s |
92.195us |
1 |
1 |
100.00
|
|
clkmgr_frequency |
9.350s |
1883.826us |
1 |
1 |
100.00
|
|
clkmgr_frequency_timeout |
5.230s |
2124.701us |
1 |
1 |
100.00
|
|
clkmgr_peri |
0.740s |
20.820us |
1 |
1 |
100.00
|
|
clkmgr_trans |
0.850s |
23.697us |
1 |
1 |
100.00
|
|
clkmgr_clk_status |
0.720s |
45.810us |
1 |
1 |
100.00
|
|
clkmgr_idle_intersig_mubi |
0.980s |
106.258us |
1 |
1 |
100.00
|
|
clkmgr_lc_ctrl_intersig_mubi |
0.950s |
146.893us |
1 |
1 |
100.00
|
|
clkmgr_lc_clk_byp_req_intersig_mubi |
0.790s |
60.161us |
1 |
1 |
100.00
|
|
clkmgr_clk_handshake_intersig_mubi |
0.960s |
18.826us |
1 |
1 |
100.00
|
|
clkmgr_div_intersig_mubi |
0.760s |
19.146us |
1 |
1 |
100.00
|
|
clkmgr_regwen |
2.680s |
765.883us |
1 |
1 |
100.00
|
|
clkmgr_shadow_reg_errors |
427.290s |
200000.000us |
0 |
1 |
0.00
|
|
clkmgr_shadow_reg_errors_with_csr_rw |
3.680s |
660.191us |
1 |
1 |
100.00
|
|
clkmgr_sec_cm |
6.380s |
2474.169us |
1 |
1 |
100.00
|
|
clkmgr_stress_all_with_rand_reset |
69.840s |
17416.002us |
1 |
1 |
100.00
|
|
clkmgr_stress_all |
9.160s |
2987.049us |
1 |
1 |
100.00
|
|
clkmgr_tl_errors |
1.620s |
72.599us |
1 |
1 |
100.00
|
|
clkmgr_tl_intg_err |
1.380s |
106.336us |
1 |
1 |
100.00
|
|
clkmgr_alert_test |
0.750s |
43.690us |
1 |
1 |
100.00
|
|
clkmgr_csr_hw_reset |
1.100s |
111.869us |
1 |
1 |
100.00
|
|
clkmgr_csr_rw |
0.790s |
37.724us |
1 |
1 |
100.00
|
|
clkmgr_csr_bit_bash |
4.170s |
260.714us |
1 |
1 |
100.00
|
|
clkmgr_csr_aliasing |
1.690s |
140.427us |
1 |
1 |
100.00
|
|
clkmgr_same_csr_outstanding |
1.190s |
64.709us |
1 |
1 |
100.00
|
|
clkmgr_csr_mem_rw_with_rand_reset |
1.230s |
44.324us |
1 |
1 |
100.00
|