Simulation Results: csrng

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.13 %
  • code
  • 92.48 %
  • assert
  • 94.76 %
  • func
  • 77.14 %
  • block
  • 97.16 %
  • line
  • 97.84 %
  • branch
  • 92.94 %
  • toggle
  • 93.44 %
  • FSM
  • 85.71 %
Validation stages
unmapped
94.74%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 18 19 94.74
csrng_smoke 3.000s 83.836us 1 1 100.00
csrng_cmds 6.000s 299.016us 1 1 100.00
csrng_stress_all 748.000s 65565.063us 1 1 100.00
csrng_intr 3.000s 52.432us 1 1 100.00
csrng_alert 8.000s 344.611us 1 1 100.00
csrng_err 2.000s 22.296us 1 1 100.00
csrng_regwen 2.000s 13.722us 1 1 100.00
csrng_stress_all_with_rand_reset 3602.000s 0.000us 0 1 0.00
csrng_sec_cm 3.000s 202.857us 1 1 100.00
csrng_tl_errors 5.000s 189.077us 1 1 100.00
csrng_tl_intg_err 5.000s 385.151us 1 1 100.00
csrng_alert_test 2.000s 26.522us 1 1 100.00
csrng_intr_test 2.000s 58.339us 1 1 100.00
csrng_csr_hw_reset 2.000s 30.236us 1 1 100.00
csrng_csr_rw 3.000s 65.547us 1 1 100.00
csrng_csr_bit_bash 13.000s 515.646us 1 1 100.00
csrng_csr_aliasing 8.000s 568.793us 1 1 100.00
csrng_same_csr_outstanding 3.000s 56.012us 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 73.556us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 73077344950824596183278457989565034228360048608350798523870977218492788457401 None