| unmapped |
|
95.24% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 20 | 21 | 95.24 | |||
| edn_smoke | 1.000s | 39.956us | 1 | 1 | 100.00 | |
| edn_regwen | 1.100s | 17.965us | 1 | 1 | 100.00 | |
| edn_genbits | 1.300s | 102.395us | 1 | 1 | 100.00 | |
| edn_stress_all | 2.380s | 143.297us | 1 | 1 | 100.00 | |
| edn_stress_all_with_rand_reset | 37.290s | 2213.190us | 1 | 1 | 100.00 | |
| edn_intr | 0.940s | 34.088us | 1 | 1 | 100.00 | |
| edn_alert | 1.130s | 100.039us | 1 | 1 | 100.00 | |
| edn_err | 1.080s | 76.898us | 1 | 1 | 100.00 | |
| edn_disable | 0.870s | 20.460us | 1 | 1 | 100.00 | |
| edn_disable_auto_req_mode | 1.860s | 500.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 3.310s | 256.419us | 1 | 1 | 100.00 | |
| edn_tl_errors | 2.930s | 421.804us | 1 | 1 | 100.00 | |
| edn_tl_intg_err | 1.380s | 53.479us | 1 | 1 | 100.00 | |
| edn_alert_test | 1.010s | 58.266us | 1 | 1 | 100.00 | |
| edn_intr_test | 0.930s | 17.964us | 1 | 1 | 100.00 | |
| edn_csr_hw_reset | 1.000s | 15.617us | 1 | 1 | 100.00 | |
| edn_csr_rw | 1.040s | 16.970us | 1 | 1 | 100.00 | |
| edn_csr_bit_bash | 2.420s | 247.374us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 1.420s | 38.193us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 1.360s | 130.462us | 1 | 1 | 100.00 | |
| edn_csr_mem_rw_with_rand_reset | 1.120s | 34.321us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| edn_disable_auto_req_mode | 5652797727085117690106457704758964472369200070338550885283680802381376106798 | 89 |
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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