Simulation Results: hmac

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.39 %
  • code
  • 97.04 %
  • assert
  • 98.02 %
  • func
  • 43.10 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.33 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 28 28 100.00
hmac_smoke 7.450s 769.480us 1 1 100.00
hmac_long_msg 46.890s 6819.277us 1 1 100.00
hmac_stress_reset 1.750s 39.073us 1 1 100.00
hmac_back_pressure 58.790s 1365.383us 1 1 100.00
hmac_datapath_stress 157.920s 2561.442us 1 1 100.00
hmac_burst_wr 2.880s 248.354us 1 1 100.00
hmac_error 67.120s 6581.123us 1 1 100.00
hmac_wipe_secret 105.310s 2694.983us 1 1 100.00
hmac_test_sha256_vectors 230.750s 33555.653us 1 1 100.00
hmac_test_sha384_vectors 21.220s 1396.396us 1 1 100.00
hmac_test_sha512_vectors 402.220s 28222.882us 1 1 100.00
hmac_test_hmac256_vectors 7.310s 243.303us 1 1 100.00
hmac_test_hmac384_vectors 7.260s 436.647us 1 1 100.00
hmac_test_hmac512_vectors 9.670s 306.015us 1 1 100.00
hmac_stress_all 9.210s 4965.847us 1 1 100.00
hmac_stress_all_with_rand_reset 14.200s 3547.943us 1 1 100.00
hmac_directed 1.330s 25.958us 1 1 100.00
hmac_sec_cm 0.990s 116.754us 1 1 100.00
hmac_tl_errors 2.260s 56.490us 1 1 100.00
hmac_tl_intg_err 2.590s 358.016us 1 1 100.00
hmac_intr_test 0.760s 102.113us 1 1 100.00
hmac_alert_test 0.650s 11.161us 1 1 100.00
hmac_csr_hw_reset 0.770s 57.932us 1 1 100.00
hmac_csr_rw 0.860s 87.727us 1 1 100.00
hmac_csr_bit_bash 4.870s 1183.941us 1 1 100.00
hmac_csr_aliasing 4.870s 838.159us 1 1 100.00
hmac_same_csr_outstanding 1.070s 141.083us 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.630s 134.918us 1 1 100.00