Simulation Results: i2c

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.57 %
  • code
  • 81.35 %
  • assert
  • 97.46 %
  • func
  • 77.91 %
  • line
  • 96.35 %
  • branch
  • 92.19 %
  • cond
  • 84.70 %
  • toggle
  • 89.45 %
  • FSM
  • 44.05 %
Validation stages
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 40 50 80.00
i2c_host_smoke 11.020s 16077.251us 1 1 100.00
i2c_host_override 0.680s 55.852us 1 1 100.00
i2c_host_fifo_watermark 161.150s 3946.388us 1 1 100.00
i2c_host_fifo_overflow 27.490s 1709.295us 1 1 100.00
i2c_host_fifo_reset_fmt 1.080s 554.071us 1 1 100.00
i2c_host_fifo_fmt_empty 3.270s 266.738us 1 1 100.00
i2c_host_fifo_reset_rx 3.470s 199.522us 1 1 100.00
i2c_host_fifo_full 33.920s 4292.781us 1 1 100.00
i2c_host_perf 46.840s 28305.409us 1 1 100.00
i2c_host_perf_precise 1.060s 101.768us 1 1 100.00
i2c_host_stretch_timeout 7.830s 667.652us 1 1 100.00
i2c_host_error_intr 2.110s 598.648us 0 1 0.00
i2c_host_stress_all 128.660s 6332.843us 0 1 0.00
i2c_target_glitch 2.360s 517.228us 0 1 0.00
i2c_target_smoke 6.550s 2562.809us 1 1 100.00
i2c_target_stress_wr 12.560s 14942.468us 1 1 100.00
i2c_target_stress_rd 29.550s 972.911us 1 1 100.00
i2c_target_stretch 4.280s 10055.423us 0 1 0.00
i2c_target_intr_smoke 4.440s 2772.662us 1 1 100.00
i2c_target_intr_stress_wr 29.700s 9532.677us 1 1 100.00
i2c_target_timeout 6.160s 17440.116us 1 1 100.00
i2c_target_unexp_stop 1.270s 57.945us 0 1 0.00
i2c_target_fifo_reset_acq 1.440s 242.370us 1 1 100.00
i2c_target_fifo_reset_tx 1.260s 209.972us 1 1 100.00
i2c_target_perf 3.950s 1603.907us 1 1 100.00
i2c_target_stress_all 28.570s 8351.197us 1 1 100.00
i2c_target_bad_addr 2.330s 1829.492us 1 1 100.00
i2c_target_hrst 20.650s 10100.349us 0 1 0.00
i2c_host_stress_all_with_rand_reset 7.000s 1696.594us 0 1 0.00
i2c_target_stress_all_with_rand_reset 0.810s 9.360us 0 1 0.00
i2c_host_mode_toggle 0.740s 11.626us 0 1 0.00
i2c_host_may_nack 12.010s 6594.311us 1 1 100.00
i2c_target_fifo_watermarks_acq 2.320s 1619.485us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.030s 283.900us 1 1 100.00
i2c_target_tx_stretch_ctrl 1.700s 59.447us 0 1 0.00
i2c_target_smbus_maxlen 2.010s 964.999us 1 1 100.00
i2c_target_nack_acqfull 1.940s 517.335us 1 1 100.00
i2c_target_nack_acqfull_addr 2.000s 2006.777us 1 1 100.00
i2c_target_nack_txstretch 1.360s 564.717us 1 1 100.00
i2c_tl_errors 2.270s 112.420us 1 1 100.00
i2c_tl_intg_err 2.200s 101.263us 1 1 100.00
i2c_sec_cm 0.980s 299.660us 1 1 100.00
i2c_intr_test 0.990s 51.317us 1 1 100.00
i2c_alert_test 0.940s 17.122us 1 1 100.00
i2c_csr_hw_reset 0.940s 77.930us 1 1 100.00
i2c_csr_rw 0.940s 47.419us 1 1 100.00
i2c_csr_bit_bash 4.200s 2051.586us 1 1 100.00
i2c_csr_aliasing 1.810s 916.830us 1 1 100.00
i2c_same_csr_outstanding 1.050s 40.390us 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.910s 29.411us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 4 test runs
i2c_host_error_intr 18028871876998421011249334681232679845981926400660562438429801720003303065470 128
UVM_INFO @ 598648187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 62261372059609102767802841625919868238065667373329147157117113870429222583197 108
UVM_INFO @ 6332843484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 17549506072324650465812559281037959170836072765141047134771975101983618987853 85
UVM_INFO @ 9359545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 102252449230825524039537330617224518125229423798424742340674709737841734861730 81
UVM_INFO @ 11626361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 38782318854639711877422987200354031497616101790795254908351761446472181313701 84
UVM_INFO @ 517228275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! 1 test run
i2c_target_stretch 25926223580219843916622586061183349263666709911147741002639823517512372244044 83
UVM_INFO @ 10055422954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 20671947049590122076014930465479048362910567007032779794617756386040354701659 83
UVM_INFO @ 57945182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 113905284014040146479535898247273890739425740735255876936241639459211695988369 79
UVM_INFO @ 10100348878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 81022194795311662519512649767207176379872629205797788852549186800355446158543 85
UVM_INFO @ 1696594194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure 1 test run
i2c_target_tx_stretch_ctrl 104644785730071515912430974113517821426781160299859464389364235288951605709349 135
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.