Simulation Results: kmac/unmasked

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.63 %
  • code
  • 88.33 %
  • assert
  • 98.50 %
  • func
  • 91.05 %
  • line
  • 97.08 %
  • branch
  • 94.50 %
  • cond
  • 91.37 %
  • toggle
  • 100.00 %
  • FSM
  • 58.68 %
Validation stages
unmapped
97.50%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 39 40 97.50
kmac_smoke 34.040s 5545.758us 1 1 100.00
kmac_long_msg_and_output 265.280s 4067.064us 1 1 100.00
kmac_sideload 161.430s 228781.190us 1 1 100.00
kmac_sideload_invalid 1.830s 45.416us 1 1 100.00
kmac_burst_write 412.780s 171888.006us 1 1 100.00
kmac_test_vectors_sha3_224 1279.940s 296460.828us 1 1 100.00
kmac_test_vectors_sha3_256 29.300s 2455.459us 1 1 100.00
kmac_test_vectors_sha3_384 18.920s 1933.555us 1 1 100.00
kmac_test_vectors_sha3_512 15.930s 4795.568us 1 1 100.00
kmac_test_vectors_shake_128 100.490s 9400.229us 1 1 100.00
kmac_test_vectors_shake_256 1961.070s 203969.505us 1 1 100.00
kmac_test_vectors_kmac 2.270s 122.419us 1 1 100.00
kmac_test_vectors_kmac_xof 2.320s 148.734us 1 1 100.00
kmac_app 49.160s 2520.005us 1 1 100.00
kmac_app_with_partial_data 203.250s 28828.881us 1 1 100.00
kmac_entropy_refresh 3.300s 560.454us 1 1 100.00
kmac_mubi 213.880s 37831.385us 1 1 100.00
kmac_error 31.100s 4463.401us 1 1 100.00
kmac_key_error 5.280s 2242.304us 1 1 100.00
kmac_edn_timeout_error 16.010s 4697.113us 1 1 100.00
kmac_entropy_mode_error 3.950s 226.553us 1 1 100.00
kmac_entropy_ready_error 14.820s 4017.870us 1 1 100.00
kmac_lc_escalation 1.330s 148.297us 1 1 100.00
kmac_stress_all 954.370s 197267.799us 1 1 100.00
kmac_stress_all_with_rand_reset 57.100s 8844.642us 0 1 0.00
kmac_sec_cm 26.650s 10616.148us 1 1 100.00
kmac_shadow_reg_errors 1.480s 64.715us 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 1.940s 487.092us 1 1 100.00
kmac_alert_test 0.800s 15.135us 1 1 100.00
kmac_mem_walk 1.070s 26.418us 1 1 100.00
kmac_mem_partial_access 1.470s 265.970us 1 1 100.00
kmac_tl_errors 2.090s 281.538us 1 1 100.00
kmac_tl_intg_err 5.160s 230.890us 1 1 100.00
kmac_intr_test 0.910s 18.807us 1 1 100.00
kmac_csr_hw_reset 1.190s 27.117us 1 1 100.00
kmac_csr_rw 0.960s 33.903us 1 1 100.00
kmac_csr_bit_bash 17.210s 1434.035us 1 1 100.00
kmac_csr_aliasing 6.690s 1832.115us 1 1 100.00
kmac_same_csr_outstanding 1.450s 67.909us 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.730s 86.789us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 21496222092143369270192568328401303785139444183073739516332229759783730895589 182
UVM_INFO @ 8844642438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---