Simulation Results: lc_ctrl/volatile_unlock_disabled

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.96 %
  • code
  • 84.14 %
  • assert
  • 94.97 %
  • func
  • 93.77 %
  • line
  • 97.19 %
  • branch
  • 93.85 %
  • cond
  • 79.36 %
  • toggle
  • 86.75 %
  • FSM
  • 63.55 %
Validation stages
unmapped
97.44%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 38 39 97.44
lc_ctrl_smoke 1.200s 19.746us 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.940s 22.002us 1 1 100.00
lc_ctrl_state_failure 8.250s 522.517us 1 1 100.00
lc_ctrl_state_post_trans 5.450s 226.857us 1 1 100.00
lc_ctrl_prog_failure 2.040s 362.007us 1 1 100.00
lc_ctrl_errors 8.780s 1951.786us 1 1 100.00
lc_ctrl_security_escalation 8.190s 1585.897us 1 1 100.00
lc_ctrl_regwen_during_op 6.340s 2194.375us 1 1 100.00
lc_ctrl_claim_transition_if 1.270s 13.362us 1 1 100.00
lc_ctrl_jtag_smoke 6.210s 272.429us 1 1 100.00
lc_ctrl_jtag_state_failure 31.500s 2880.132us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.080s 1454.617us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.310s 418.919us 1 1 100.00
lc_ctrl_jtag_errors 12.970s 7006.611us 1 1 100.00
lc_ctrl_jtag_access 14.550s 2774.417us 1 1 100.00
lc_ctrl_jtag_priority 8.930s 1236.901us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.560s 1409.607us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.100s 79.595us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.510s 34.108us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.590s 1061.764us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.750s 644.179us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.640s 93.750us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.480s 2777.568us 1 1 100.00
lc_ctrl_jtag_alert_test 1.680s 46.881us 1 1 100.00
lc_ctrl_sec_mubi 12.230s 539.416us 1 1 100.00
lc_ctrl_sec_token_mux 8.380s 1563.876us 1 1 100.00
lc_ctrl_sec_token_digest 6.360s 271.163us 1 1 100.00
lc_ctrl_stress_all 62.130s 24021.094us 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 42.330s 3695.904us 0 1 0.00
lc_ctrl_sec_cm 7.710s 478.203us 1 1 100.00
lc_ctrl_tl_errors 2.420s 37.923us 1 1 100.00
lc_ctrl_tl_intg_err 1.850s 119.202us 1 1 100.00
lc_ctrl_alert_test 1.320s 41.717us 1 1 100.00
lc_ctrl_csr_hw_reset 1.050s 43.183us 1 1 100.00
lc_ctrl_csr_rw 1.040s 24.537us 1 1 100.00
lc_ctrl_csr_bit_bash 1.620s 22.098us 1 1 100.00
lc_ctrl_csr_aliasing 1.760s 91.796us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.250s 29.463us 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.790s 31.246us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all_with_rand_reset 114660980150845745398523830796496431433897439338585769322734194284682714725856 14293
UVM_INFO @ 3695904321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---