Simulation Results: lc_ctrl/volatile_unlock_enabled

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.42 %
  • code
  • 83.95 %
  • assert
  • 94.97 %
  • func
  • 92.35 %
  • line
  • 97.17 %
  • branch
  • 93.52 %
  • cond
  • 79.61 %
  • toggle
  • 88.72 %
  • FSM
  • 60.75 %
Validation stages
unmapped
97.44%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 38 39 97.44
lc_ctrl_smoke 1.070s 53.257us 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.930s 24.302us 1 1 100.00
lc_ctrl_state_failure 8.210s 1067.584us 1 1 100.00
lc_ctrl_state_post_trans 4.700s 225.287us 1 1 100.00
lc_ctrl_prog_failure 2.840s 87.350us 1 1 100.00
lc_ctrl_errors 4.380s 297.367us 1 1 100.00
lc_ctrl_security_escalation 7.570s 281.668us 1 1 100.00
lc_ctrl_regwen_during_op 7.250s 1565.228us 1 1 100.00
lc_ctrl_claim_transition_if 0.920s 35.337us 1 1 100.00
lc_ctrl_jtag_smoke 11.260s 635.277us 1 1 100.00
lc_ctrl_jtag_state_failure 65.070s 36787.482us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.280s 2624.118us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.340s 65.309us 1 1 100.00
lc_ctrl_jtag_errors 36.190s 1836.971us 1 1 100.00
lc_ctrl_jtag_access 12.110s 635.685us 1 1 100.00
lc_ctrl_jtag_priority 3.860s 384.170us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.070s 1132.104us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.320s 190.736us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.950s 37.510us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.690s 410.998us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.440s 2429.096us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.340s 39.008us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.690s 103.710us 1 1 100.00
lc_ctrl_jtag_alert_test 1.120s 41.824us 1 1 100.00
lc_ctrl_sec_mubi 5.850s 755.012us 1 1 100.00
lc_ctrl_sec_token_mux 3.410s 793.863us 1 1 100.00
lc_ctrl_sec_token_digest 8.350s 2353.331us 1 1 100.00
lc_ctrl_stress_all 41.940s 2316.998us 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 45.600s 8643.615us 0 1 0.00
lc_ctrl_sec_cm 7.710s 1529.058us 1 1 100.00
lc_ctrl_tl_errors 2.050s 33.340us 1 1 100.00
lc_ctrl_tl_intg_err 2.160s 407.015us 1 1 100.00
lc_ctrl_alert_test 1.080s 27.844us 1 1 100.00
lc_ctrl_csr_hw_reset 0.860s 16.771us 1 1 100.00
lc_ctrl_csr_rw 0.840s 47.279us 1 1 100.00
lc_ctrl_csr_bit_bash 1.380s 88.051us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 243.708us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.240s 110.774us 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.250s 200.159us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 9490582303386489199848654608390048319388722173559962256338298554764964820845 5706
UVM_INFO @ 8643615334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---