| unmapped |
|
90.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 27 | 30 | 90.00 | |||
| otp_ctrl_wake_up | 1.560s | 802.367us | 1 | 1 | 100.00 | |
| otp_ctrl_smoke | 3.140s | 321.559us | 1 | 1 | 100.00 | |
| otp_ctrl_partition_walk | 12.040s | 513.782us | 1 | 1 | 100.00 | |
| otp_ctrl_low_freq_read | 9.310s | 3114.308us | 1 | 1 | 100.00 | |
| otp_ctrl_init_fail | 3.890s | 683.899us | 1 | 1 | 100.00 | |
| otp_ctrl_background_chks | 13.250s | 2362.976us | 1 | 1 | 100.00 | |
| otp_ctrl_parallel_lc_req | 20.320s | 12177.902us | 1 | 1 | 100.00 | |
| otp_ctrl_parallel_lc_esc | 17.770s | 1562.420us | 1 | 1 | 100.00 | |
| otp_ctrl_dai_lock | 9.330s | 696.064us | 1 | 1 | 100.00 | |
| otp_ctrl_dai_errs | 17.280s | 3026.214us | 1 | 1 | 100.00 | |
| otp_ctrl_check_fail | 8.780s | 6464.900us | 1 | 1 | 100.00 | |
| otp_ctrl_macro_errs | 3.990s | 624.265us | 0 | 1 | 0.00 | |
| otp_ctrl_parallel_key_req | 7.670s | 373.518us | 1 | 1 | 100.00 | |
| otp_ctrl_regwen | 5.550s | 2494.863us | 1 | 1 | 100.00 | |
| otp_ctrl_test_access | 3.950s | 353.475us | 1 | 1 | 100.00 | |
| otp_ctrl_stress_all_with_rand_reset | 38.020s | 3841.850us | 0 | 1 | 0.00 | |
| otp_ctrl_stress_all | 267.960s | 55495.883us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 124.330s | 13948.417us | 1 | 1 | 100.00 | |
| otp_ctrl_tl_errors | 2.690s | 56.524us | 1 | 1 | 100.00 | |
| otp_ctrl_tl_intg_err | 14.980s | 1616.752us | 1 | 1 | 100.00 | |
| otp_ctrl_alert_test | 1.660s | 211.808us | 1 | 1 | 100.00 | |
| otp_ctrl_intr_test | 1.420s | 73.209us | 1 | 1 | 100.00 | |
| otp_ctrl_mem_walk | 1.340s | 556.174us | 1 | 1 | 100.00 | |
| otp_ctrl_mem_partial_access | 1.210s | 39.720us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_hw_reset | 1.960s | 110.255us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_rw | 1.420s | 109.483us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_bit_bash | 3.530s | 85.672us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 2.930s | 118.091us | 1 | 1 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 2.760s | 219.385us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_mem_rw_with_rand_reset | 2.130s | 115.604us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* | 1 test run | |||
| otp_ctrl_macro_errs | 109043233130336340255605716691534393524154711497643812871695661628471660427806 | 1686 |
UVM_INFO @ 624264768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen | 1 test run | |||
| otp_ctrl_stress_all_with_rand_reset | 69463056816107722057121925645173727079796611361453787246343643221419223736663 | 8466 |
UVM_INFO @ 3841849575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | 1 test run | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 103435356979853768854940259942787478850720006377938387618495596941279634895803 | 98 |
UVM_INFO @ 115604146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|