Simulation Results: rom_ctrl/32kb

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.06 %
  • code
  • 99.30 %
  • assert
  • 96.80 %
  • func
  • 98.09 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 97.62 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rom_ctrl_smoke 3.610s 427.614us 1 1 100.00
rom_ctrl_stress_all 11.950s 558.348us 1 1 100.00
rom_ctrl_max_throughput_chk 5.130s 134.511us 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 83.960s 12527.673us 1 1 100.00
rom_ctrl_kmac_err_chk 6.470s 1328.482us 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 44.480s 7958.948us 1 1 100.00
rom_ctrl_sec_cm 105.710s 1133.964us 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.360s 16634.497us 1 1 100.00
rom_ctrl_tl_errors 6.550s 154.730us 1 1 100.00
rom_ctrl_tl_intg_err 45.900s 327.596us 1 1 100.00
rom_ctrl_alert_test 3.550s 2096.770us 1 1 100.00
rom_ctrl_mem_walk 4.000s 127.328us 1 1 100.00
rom_ctrl_mem_partial_access 3.610s 483.413us 1 1 100.00
rom_ctrl_csr_hw_reset 5.210s 172.962us 1 1 100.00
rom_ctrl_csr_rw 3.750s 1418.004us 1 1 100.00
rom_ctrl_csr_bit_bash 3.960s 127.250us 1 1 100.00
rom_ctrl_csr_aliasing 4.170s 169.135us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.470s 370.845us 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.430s 278.484us 1 1 100.00