Simulation Results: rstmgr

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.87 %
  • code
  • 99.18 %
  • assert
  • 98.66 %
  • func
  • 95.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.12 %
  • toggle
  • 99.25 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rstmgr_smoke 1.330s 251.661us 1 1 100.00
rstmgr_por_stretcher 0.970s 127.356us 1 1 100.00
rstmgr_reset 3.740s 983.204us 1 1 100.00
rstmgr_sw_rst_reset_race 1.390s 148.525us 1 1 100.00
rstmgr_sw_rst 1.690s 154.581us 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.240s 194.622us 1 1 100.00
rstmgr_leaf_rst_cnsty 7.400s 2670.641us 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.030s 306.651us 1 1 100.00
rstmgr_stress_all 1.720s 456.915us 1 1 100.00
rstmgr_sec_cm 9.790s 8565.676us 1 1 100.00
rstmgr_tl_errors 1.810s 322.874us 1 1 100.00
rstmgr_tl_intg_err 1.550s 497.374us 1 1 100.00
rstmgr_alert_test 0.760s 62.619us 1 1 100.00
rstmgr_csr_hw_reset 0.910s 100.287us 1 1 100.00
rstmgr_csr_rw 0.800s 67.414us 1 1 100.00
rstmgr_csr_bit_bash 4.250s 1168.083us 1 1 100.00
rstmgr_csr_aliasing 1.330s 219.455us 1 1 100.00
rstmgr_same_csr_outstanding 1.060s 151.448us 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.130s 156.027us 1 1 100.00