Simulation Results: rv_timer

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.84 %
  • code
  • 99.77 %
  • assert
  • 98.41 %
  • func
  • 92.35 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.08 %
  • toggle
  • 100.00 %
Validation stages
unmapped
78.95%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 15 19 78.95
rv_timer_random 0.990s 757.231us 1 1 100.00
rv_timer_min 0.750s 159.629us 0 1 0.00
rv_timer_max 0.670s 57.063us 0 1 0.00
rv_timer_disabled 1.640s 1001.939us 1 1 100.00
rv_timer_cfg_update_on_fly 315.020s 712005.802us 1 1 100.00
rv_timer_random_reset 0.650s 110.962us 0 1 0.00
rv_timer_stress_all_with_rand_reset 30.220s 15983.540us 0 1 0.00
rv_timer_stress_all 2.540s 6038.542us 1 1 100.00
rv_timer_sec_cm 0.930s 87.521us 1 1 100.00
rv_timer_tl_errors 1.250s 319.288us 1 1 100.00
rv_timer_tl_intg_err 0.820s 343.031us 1 1 100.00
rv_timer_intr_test 0.580s 15.337us 1 1 100.00
rv_timer_alert_test 0.680s 15.636us 1 1 100.00
rv_timer_csr_hw_reset 0.590s 15.198us 1 1 100.00
rv_timer_csr_rw 0.600s 14.333us 1 1 100.00
rv_timer_csr_bit_bash 1.140s 660.554us 1 1 100.00
rv_timer_csr_aliasing 0.970s 41.260us 1 1 100.00
rv_timer_same_csr_outstanding 0.760s 57.716us 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.820s 57.082us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 24533540766076470617350592088866695151687611391425507483409425699198532093922 75
UVM_INFO @ 159629316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 23420545180703529479950644517386667123190854165765874442643594329797713841375 75
UVM_INFO @ 110962331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 113246044544457468650621504166748496146549525457638677677938562944021462918159 75
UVM_INFO @ 57063399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 74517485427490679743210220420727298628829392541517802310423197098959716337814 285
UVM_INFO @ 15983540439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---