Simulation Results: spi_host

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.35 %
  • code
  • 95.03 %
  • assert
  • 96.78 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 26 26 100.00
spi_host_smoke 26.000s 3026.070us 1 1 100.00
spi_host_speed 3.000s 168.716us 1 1 100.00
spi_host_upper_range_clkdiv 59.000s 2303.146us 1 1 100.00
spi_host_performance 2.000s 26.034us 1 1 100.00
spi_host_sw_reset 4.000s 237.524us 1 1 100.00
spi_host_overflow_underflow 2.000s 108.486us 1 1 100.00
spi_host_error_cmd 1.000s 56.856us 1 1 100.00
spi_host_event 33.000s 1402.521us 1 1 100.00
spi_host_passthrough_mode 1.000s 26.818us 1 1 100.00
spi_host_status_stall 15.000s 474.221us 1 1 100.00
spi_host_idlecsbactive 8.000s 5207.574us 1 1 100.00
spi_host_stress_all 8.000s 704.563us 1 1 100.00
spi_host_spien 3.000s 557.059us 1 1 100.00
spi_host_tl_errors 2.000s 993.846us 1 1 100.00
spi_host_tl_intg_err 1.000s 43.294us 1 1 100.00
spi_host_sec_cm 1.000s 350.964us 1 1 100.00
spi_host_intr_test 1.000s 21.501us 1 1 100.00
spi_host_alert_test 1.000s 47.771us 1 1 100.00
spi_host_mem_walk 1.000s 14.377us 1 1 100.00
spi_host_mem_partial_access 1.000s 25.069us 1 1 100.00
spi_host_csr_hw_reset 1.000s 140.268us 1 1 100.00
spi_host_csr_rw 1.000s 30.676us 1 1 100.00
spi_host_csr_bit_bash 3.000s 3118.743us 1 1 100.00
spi_host_csr_aliasing 1.000s 42.022us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 57.275us 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 71.898us 1 1 100.00