Simulation Results

unmapped

31/31 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				31	31	100.00
	sram_ctrl_smoke	2.000s	2583.789us	1	1	100.00
	sram_ctrl_multiple_keys	18.000s	31289.666us	1	1	100.00
	sram_ctrl_bijection	170.000s	231242.262us	1	1	100.00
	sram_ctrl_stress_pipeline	149.000s	3873.021us	1	1	100.00
	sram_ctrl_partial_access	3.000s	376.151us	1	1	100.00
	sram_ctrl_partial_access_b2b	178.000s	65284.691us	1	1	100.00
	sram_ctrl_max_throughput	4.000s	674.490us	1	1	100.00
	sram_ctrl_throughput_w_partial_write	4.000s	706.431us	1	1	100.00
	sram_ctrl_throughput_w_readback	5.000s	4787.667us	1	1	100.00
	sram_ctrl_lc_escalation	47.000s	14461.449us	1	1	100.00
	sram_ctrl_access_during_key_req	39.000s	17250.891us	1	1	100.00
	sram_ctrl_executable	10.000s	1842.428us	1	1	100.00
	sram_ctrl_regwen	6.000s	2572.165us	1	1	100.00
	sram_ctrl_ram_cfg	3.000s	357.419us	1	1	100.00
	sram_ctrl_mem_walk	219.000s	84782.597us	1	1	100.00
	sram_ctrl_mem_partial_access	50.000s	3110.891us	1	1	100.00
	sram_ctrl_readback_err	4.000s	1366.581us	1	1	100.00
	sram_ctrl_mubi_enc_err	3.000s	671.571us	1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	25.000s	5831.216us	1	1	100.00
	sram_ctrl_stress_all	248.000s	133143.017us	1	1	100.00
	sram_ctrl_sec_cm	4.000s	2399.136us	1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	11.000s	3708.271us	1	1	100.00
	sram_ctrl_tl_errors	3.000s	62.317us	1	1	100.00
	sram_ctrl_tl_intg_err	2.000s	210.819us	1	1	100.00
	sram_ctrl_alert_test	1.000s	39.846us	1	1	100.00
	sram_ctrl_csr_hw_reset	1.000s	154.106us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	20.962us	1	1	100.00
	sram_ctrl_csr_bit_bash	2.000s	88.350us	1	1	100.00
	sram_ctrl_csr_aliasing	2.000s	21.427us	1	1	100.00
	sram_ctrl_same_csr_outstanding	1.000s	18.799us	1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	3.000s	347.422us	1	1	100.00

Simulation Results: sram_ctrl/main