Simulation Results

unmapped

31/31 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				31	31	100.00
	sram_ctrl_smoke	3.000s	243.388us	1	1	100.00
	sram_ctrl_multiple_keys	3.000s	328.912us	1	1	100.00
	sram_ctrl_bijection	5.000s	460.490us	1	1	100.00
	sram_ctrl_stress_pipeline	134.000s	2801.234us	1	1	100.00
	sram_ctrl_partial_access	2.000s	95.086us	1	1	100.00
	sram_ctrl_partial_access_b2b	112.000s	15133.638us	1	1	100.00
	sram_ctrl_max_throughput	2.000s	149.183us	1	1	100.00
	sram_ctrl_throughput_w_partial_write	1.000s	126.750us	1	1	100.00
	sram_ctrl_throughput_w_readback	2.000s	82.533us	1	1	100.00
	sram_ctrl_lc_escalation	7.000s	763.778us	1	1	100.00
	sram_ctrl_access_during_key_req	5.000s	242.900us	1	1	100.00
	sram_ctrl_executable	8.000s	318.937us	1	1	100.00
	sram_ctrl_regwen	5.000s	342.429us	1	1	100.00
	sram_ctrl_ram_cfg	1.000s	48.457us	1	1	100.00
	sram_ctrl_mem_walk	6.000s	652.536us	1	1	100.00
	sram_ctrl_mem_partial_access	3.000s	220.475us	1	1	100.00
	sram_ctrl_readback_err	1.000s	37.848us	1	1	100.00
	sram_ctrl_mubi_enc_err	1.000s	95.081us	1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	54.000s	16658.561us	1	1	100.00
	sram_ctrl_stress_all	51.000s	5051.980us	1	1	100.00
	sram_ctrl_sec_cm	2.000s	696.175us	1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.000s	454.697us	1	1	100.00
	sram_ctrl_tl_errors	2.000s	105.525us	1	1	100.00
	sram_ctrl_tl_intg_err	2.000s	155.667us	1	1	100.00
	sram_ctrl_alert_test	1.000s	16.640us	1	1	100.00
	sram_ctrl_csr_hw_reset	1.000s	31.459us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	15.118us	1	1	100.00
	sram_ctrl_csr_bit_bash	3.000s	207.035us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	33.853us	1	1	100.00
	sram_ctrl_same_csr_outstanding	2.000s	18.319us	1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.000s	48.423us	1	1	100.00

Simulation Results: sram_ctrl/ret