Simulation Results: sysrst_ctrl

 
01/06/2026 15:30:27 DVSim: v1.49.6 sha: 12b260e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.17 %
  • code
  • 93.50 %
  • assert
  • 95.31 %
  • func
  • 63.70 %
  • line
  • 97.73 %
  • branch
  • 97.81 %
  • cond
  • 95.02 %
  • toggle
  • 100.00 %
  • FSM
  • 76.92 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 27 27 100.00
sysrst_ctrl_smoke 4.970s 2110.394us 1 1 100.00
sysrst_ctrl_in_out_inverted 5.530s 2461.798us 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.970s 2174.797us 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.010s 2523.962us 1 1 100.00
sysrst_ctrl_pin_access_test 1.290s 2270.401us 1 1 100.00
sysrst_ctrl_pin_override_test 1.850s 2528.172us 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.700s 2614.796us 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 4.410s 3694.088us 1 1 100.00
sysrst_ctrl_auto_blk_key_output 151.850s 319640.175us 1 1 100.00
sysrst_ctrl_ultra_low_pwr 5.150s 9018.567us 1 1 100.00
sysrst_ctrl_combo_detect 127.060s 132988.524us 1 1 100.00
sysrst_ctrl_edge_detect 9.440s 5788.598us 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 44.510s 22828.746us 1 1 100.00
sysrst_ctrl_feature_disable 37.220s 41352.182us 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.490s 3687.021us 1 1 100.00
sysrst_ctrl_stress_all 6.840s 15668.806us 1 1 100.00
sysrst_ctrl_sec_cm 24.410s 22027.028us 1 1 100.00
sysrst_ctrl_tl_errors 4.970s 2046.902us 1 1 100.00
sysrst_ctrl_tl_intg_err 19.420s 43046.315us 1 1 100.00
sysrst_ctrl_alert_test 4.570s 2012.795us 1 1 100.00
sysrst_ctrl_intr_test 1.580s 2043.597us 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.790s 6136.093us 1 1 100.00
sysrst_ctrl_csr_rw 2.410s 2134.361us 1 1 100.00
sysrst_ctrl_csr_bit_bash 25.320s 41299.814us 1 1 100.00
sysrst_ctrl_csr_aliasing 8.480s 3202.153us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.440s 8857.718us 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.980s 2064.956us 1 1 100.00