Simulation Results: adc_ctrl

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.01 %
  • code
  • 93.72 %
  • assert
  • 88.17 %
  • func
  • 13.14 %
  • line
  • 97.97 %
  • branch
  • 96.23 %
  • cond
  • 85.94 %
  • toggle
  • 99.29 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 9.950s 5824.363us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.500s 798.296us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.860s 443.525us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 4.260s 12161.510us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.720s 491.308us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.040s 353.160us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.860s 443.525us 1 1 100.00
adc_ctrl_csr_aliasing 1.720s 491.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.140s 354.017us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.650s 300.869us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.090s 405.234us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.350s 526.671us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.140s 504.407us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 1.340s 463.999us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.320s 478.985us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.920s 357.431us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.560s 3905.527us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 48.150s 29622.990us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 156.000s 96020.327us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.420s 943.100us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.010s 338.420us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.110s 344.545us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.390s 414.404us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.390s 414.404us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.500s 798.296us 1 1 100.00
adc_ctrl_csr_rw 0.860s 443.525us 1 1 100.00
adc_ctrl_csr_aliasing 1.720s 491.308us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.680s 2596.307us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.500s 798.296us 1 1 100.00
adc_ctrl_csr_rw 0.860s 443.525us 1 1 100.00
adc_ctrl_csr_aliasing 1.720s 491.308us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.680s 2596.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.420s 3648.423us 1 1 100.00
adc_ctrl_tl_intg_err 1.660s 4466.356us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 1.660s 4466.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.890s 755.466us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 34766400909634903794531286146772720555249811064930266565932916493813725980744 388
UVM_INFO @ 354017177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 24794818199098176229809458629496923444201682014340922538381860947366733260650 388
UVM_INFO @ 300869289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 86953970466172882566890397810274456909745276294714596823754352366358366098168 388
UVM_INFO @ 405233983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 13295192753294275610638423126596337471652652158449840170261253217176995917982 388
UVM_INFO @ 526671358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 17294647070224567343537070235492016190880881451949469083267451142328426437614 388
UVM_INFO @ 504407125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 97104792993728984128848057444411984552521414459815464571552735686036027002718 388
UVM_INFO @ 463998755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 56856361177588975455058322275315163756262835478809482985557736969640940488228 388
UVM_INFO @ 357431351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 93495965175012242276019029600122567935248466097497910480293273434409335510429 388
UVM_INFO @ 478984611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 29345607758717473843843868511574853309744566379129166592754022677955344229525 408
UVM_INFO @ 755466224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 22537179361164297788501446479190335887107382973258667351732521031286642154821 389
UVM_INFO @ 943099879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---