Simulation Results: aes/unmasked

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.65 %
  • code
  • 89.59 %
  • assert
  • 97.73 %
  • func
  • 75.63 %
  • block
  • 90.20 %
  • line
  • 92.62 %
  • branch
  • 81.18 %
  • toggle
  • 97.90 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 138.500us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 83.526us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 85.121us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 79.297us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 1378.422us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 184.257us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 118.539us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 79.297us 1 1 100.00
aes_csr_aliasing 2.000s 184.257us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 83.526us 1 1 100.00
aes_config_error 1.000s 56.551us 1 1 100.00
aes_stress 3.000s 135.009us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 83.526us 1 1 100.00
aes_config_error 1.000s 56.551us 1 1 100.00
aes_stress 3.000s 135.009us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 135.009us 1 1 100.00
aes_b2b 3.000s 73.940us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 135.009us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 83.526us 1 1 100.00
aes_config_error 1.000s 56.551us 1 1 100.00
aes_stress 3.000s 135.009us 1 1 100.00
aes_alert_reset 2.000s 264.296us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 64.436us 1 1 100.00
aes_config_error 1.000s 56.551us 1 1 100.00
aes_alert_reset 2.000s 264.296us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 98.315us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 245.774us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 264.296us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 135.009us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 135.009us 1 1 100.00
aes_sideload 2.000s 79.910us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 86.550us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 23.000s 1764.111us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 94.888us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 252.431us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 252.431us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 85.121us 1 1 100.00
aes_csr_rw 2.000s 79.297us 1 1 100.00
aes_csr_aliasing 2.000s 184.257us 1 1 100.00
aes_same_csr_outstanding 2.000s 239.816us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 85.121us 1 1 100.00
aes_csr_rw 2.000s 79.297us 1 1 100.00
aes_csr_aliasing 2.000s 184.257us 1 1 100.00
aes_same_csr_outstanding 2.000s 239.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 179.122us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 165.587us 1 1 100.00
aes_control_fi 2.000s 58.586us 1 1 100.00
aes_cipher_fi 2.000s 47.265us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 133.549us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 133.549us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 133.549us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 133.549us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 258.959us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1159.777us 1 1 100.00
aes_tl_intg_err 1.000s 193.052us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 193.052us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 264.296us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 133.549us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 133.549us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 83.526us 1 1 100.00
aes_stress 3.000s 135.009us 1 1 100.00
aes_alert_reset 2.000s 264.296us 1 1 100.00
aes_core_fi 1.000s 76.625us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 1.000s 56.551us 1 1 100.00
aes_stress 3.000s 135.009us 1 1 100.00
aes_core_fi 1.000s 76.625us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 133.549us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 120.653us 1 1 100.00
aes_stress 3.000s 135.009us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 135.009us 1 1 100.00
aes_sideload 2.000s 79.910us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 120.653us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 120.653us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 120.653us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 120.653us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 120.653us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 135.009us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 135.009us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 165.587us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 165.587us 1 1 100.00
aes_control_fi 2.000s 58.586us 1 1 100.00
aes_cipher_fi 2.000s 47.265us 1 1 100.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 165.587us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 165.587us 1 1 100.00
aes_control_fi 2.000s 58.586us 1 1 100.00
aes_cipher_fi 2.000s 47.265us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 47.265us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 165.587us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 165.587us 1 1 100.00
aes_control_fi 2.000s 58.586us 1 1 100.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 165.587us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 165.587us 1 1 100.00
aes_control_fi 2.000s 58.586us 1 1 100.00
aes_cipher_fi 2.000s 47.265us 1 1 100.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 264.296us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 165.587us 1 1 100.00
aes_control_fi 2.000s 58.586us 1 1 100.00
aes_cipher_fi 2.000s 47.265us 1 1 100.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 165.587us 1 1 100.00
aes_control_fi 2.000s 58.586us 1 1 100.00
aes_cipher_fi 2.000s 47.265us 1 1 100.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 165.587us 1 1 100.00
aes_control_fi 2.000s 58.586us 1 1 100.00
aes_ctr_fi 2.000s 95.677us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 3.000s 165.587us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 165.587us 1 1 100.00
aes_control_fi 2.000s 58.586us 1 1 100.00
aes_cipher_fi 2.000s 47.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 13.000s 912.928us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:1031) virtual_sequencer [aes_alert_reset_vseq] 1 test run
aes_stress_all_with_rand_reset 6176859758233586134497329497130278723416665759845341520814482746800008506031 871
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0