Simulation Results: alert_handler

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.26 %
  • code
  • 92.75 %
  • assert
  • 98.33 %
  • func
  • 79.69 %
  • line
  • 99.79 %
  • branch
  • 98.47 %
  • cond
  • 91.44 %
  • toggle
  • 90.16 %
  • FSM
  • 83.87 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 34.750s 8643.330us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.440s 653.917us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.100s 223.481us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 156.380s 4984.070us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 35.830s 10709.491us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.460s 40.631us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.100s 223.481us 1 1 100.00
alert_handler_csr_aliasing 35.830s 10709.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 82.880s 2667.834us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 6.950s 387.069us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1705.530s 46613.118us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 5.370s 127.815us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 34.750s 8643.330us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 14.940s 248.507us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 6.020s 171.017us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 30.950s 5142.118us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2158.570s 119004.000us 1 1 100.00
alert_handler_lpg_stub_clk 1876.880s 55229.421us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 550.360s 10692.526us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 3.850s 340.279us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.370s 186.899us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.190s 14.675us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 2.860s 134.914us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 2.860s 134.914us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.440s 653.917us 1 1 100.00
alert_handler_csr_rw 3.100s 223.481us 1 1 100.00
alert_handler_csr_aliasing 35.830s 10709.491us 1 1 100.00
alert_handler_same_csr_outstanding 6.140s 309.925us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.440s 653.917us 1 1 100.00
alert_handler_csr_rw 3.100s 223.481us 1 1 100.00
alert_handler_csr_aliasing 35.830s 10709.491us 1 1 100.00
alert_handler_same_csr_outstanding 6.140s 309.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 179.460s 17915.578us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 179.460s 17915.578us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 179.460s 17915.578us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 179.460s 17915.578us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 683.220s 50404.235us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 74.210s 3046.441us 1 1 100.00
alert_handler_tl_intg_err 2.120s 124.313us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.120s 124.313us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 179.460s 17915.578us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 34.750s 8643.330us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 34.750s 8643.330us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 34.750s 8643.330us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 34.750s 8643.330us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 5.370s 127.815us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2158.570s 119004.000us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 5.370s 127.815us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1705.530s 46613.118us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1705.530s 46613.118us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 74.210s 3046.441us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 74.210s 3046.441us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 74.210s 3046.441us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 74.210s 3046.441us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 74.210s 3046.441us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 74.210s 3046.441us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 74.210s 3046.441us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 74.210s 3046.441us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 74.210s 3046.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 7.580s 194.391us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 42229216067670883486753084141257488621437313484271782144967135362748270597369 87
UVM_INFO @ 5142118191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 71409590498409938248537991621603050233150952229974354083458505506972887569232 128
UVM_INFO @ 340279209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 9590697364193919774499017745792685368546245940016423682624971664092900530297 92
UVM_INFO @ 194391096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---