Simulation Results

Simulation Results: chip

04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
72.21 %

code
84.59 %

assert
97.25 %

func
34.80 %

line
93.99 %

branch
92.37 %

cond
88.09 %

toggle
91.34 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		76.98%
V2S		100.00%
V3		65.38%
unmapped		63.64%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	177.810s	3487.876us	1	1	100.00
	chip_sw_example_rom	76.390s	2384.083us	1	1	100.00
	chip_sw_example_manufacturer	173.800s	3686.206us	1	1	100.00
	chip_sw_example_concurrency	149.880s	2885.524us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	304.860s	7179.586us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	457.420s	6264.874us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	372.180s	6165.045us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4124.710s	35829.059us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	645.500s	9549.461us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4124.710s	35829.059us	1	1	100.00
	chip_csr_rw	457.420s	6264.874us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	4.060s	42.946us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	304.170s	4317.421us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	304.170s	4317.421us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	304.170s	4317.421us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	381.390s	4937.189us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	381.390s	4937.189us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	357.070s	4538.227us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	359.950s	4679.033us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	371.260s	4738.126us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1093.570s	9377.805us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	352.060s	3987.137us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1032.160s	13564.767us	1	1	100.00

214/278 passed

76.98 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	171.540s	4812.119us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	171.540s	4812.119us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				0	1	0.00
	chip_sw_sleep_pin_mio_dio_val	224.190s	3569.400us	0	1	0.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	351.360s	6583.940us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	158.440s	3539.905us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	192.450s	3751.430us	1	1	100.00
	chip_tap_straps_testunlock0	251.960s	4884.678us	1	1	100.00
	chip_tap_straps_rma	326.720s	7030.874us	1	1	100.00
	chip_tap_straps_prod	112.980s	2841.940us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	151.500s	2493.037us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	770.100s	9570.505us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	392.770s	5509.255us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	392.770s	5509.255us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	754.140s	8014.143us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1683.790s	14465.606us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	409.870s	4835.007us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	585.430s	6418.618us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3919.070s	18598.029us	1	1	100.00
	chip_sw_aes_enc_jitter_en	182.950s	3021.194us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	785.190s	7944.609us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	171.410s	3133.610us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1152.790s	10114.719us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	179.550s	2799.901us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	342.760s	5298.976us	1	1	100.00
	chip_sw_clkmgr_jitter	133.820s	2458.287us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	187.260s	3332.035us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	573.500s	8305.685us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	220.120s	4958.890us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	147.310s	3560.408us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	220.120s	4958.890us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	133.560s	3043.491us	1	1	100.00
	chip_sw_aes_smoketest	204.370s	2863.234us	1	1	100.00
	chip_sw_aon_timer_smoketest	189.450s	3312.854us	1	1	100.00
	chip_sw_clkmgr_smoketest	174.900s	3101.971us	1	1	100.00
	chip_sw_csrng_smoketest	147.600s	2305.249us	1	1	100.00
	chip_sw_entropy_src_smoketest	850.290s	7508.339us	1	1	100.00
	chip_sw_gpio_smoketest	184.050s	3152.119us	1	1	100.00
	chip_sw_hmac_smoketest	231.930s	3941.995us	1	1	100.00
	chip_sw_kmac_smoketest	183.390s	3060.704us	1	1	100.00
	chip_sw_otbn_smoketest	1482.910s	10038.195us	1	1	100.00
	chip_sw_pwrmgr_smoketest	265.610s	6668.029us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	274.570s	5474.325us	1	1	100.00
	chip_sw_rv_plic_smoketest	167.640s	3364.584us	1	1	100.00
	chip_sw_rv_timer_smoketest	144.790s	3017.361us	1	1	100.00
	chip_sw_rstmgr_smoketest	164.700s	2960.980us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	133.130s	2999.802us	1	1	100.00
	chip_sw_uart_smoketest	172.800s	2896.089us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	140.590s	3131.384us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	250.620s	4178.852us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	8105.490s	63973.569us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3167.770s	15420.294us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	81.390s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	193.730s	3758.620us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	206.920s	3978.155us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7229.030s	54803.403us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7253.470s	58571.627us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	64.280s	2283.776us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	64.280s	2283.776us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4124.710s	35829.059us	1	1	100.00
	chip_same_csr_outstanding	1249.280s	15574.641us	1	1	100.00
	chip_csr_hw_reset	304.860s	7179.586us	1	1	100.00
	chip_csr_rw	457.420s	6264.874us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4124.710s	35829.059us	1	1	100.00
	chip_same_csr_outstanding	1249.280s	15574.641us	1	1	100.00
	chip_csr_hw_reset	304.860s	7179.586us	1	1	100.00
	chip_csr_rw	457.420s	6264.874us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	21.250s	930.582us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	5.200s	49.018us	1	1	100.00
	xbar_smoke_large_delays	48.110s	7714.234us	1	1	100.00
	xbar_smoke_slow_rsp	51.480s	4955.113us	1	1	100.00
	xbar_random_zero_delays	12.280s	234.293us	1	1	100.00
	xbar_random_large_delays	143.470s	25207.434us	1	1	100.00
	xbar_random_slow_rsp	239.190s	28918.111us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	10.070s	116.991us	1	1	100.00
	xbar_error_and_unmapped_addr	19.090s	719.682us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	17.680s	880.375us	1	1	100.00
	xbar_error_and_unmapped_addr	19.090s	719.682us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	10.210s	257.048us	1	1	100.00
	xbar_access_same_device_slow_rsp	655.620s	74713.276us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	24.130s	1421.248us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	67.910s	1326.990us	1	1	100.00
	xbar_stress_all_with_error	17.990s	209.337us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	108.580s	450.131us	1	1	100.00
	xbar_stress_all_with_reset_error	11.580s	50.372us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3167.770s	15420.294us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2664.540s	27670.723us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3050.650s	14958.601us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	21.200s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	49.473s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	45.153s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	26.258s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	13.176s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	168.926s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	62.605s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	71.297s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	61.440s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	62.168s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	152.902s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	120.233s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	164.138s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	191.156s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	93.457s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.800s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	20.590s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	19.940s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	19.730s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	19.330s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	19.730s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	21.660s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.380s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.160s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	18.090s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	18.860s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.540s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.900s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.610s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.920s	10.200us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	24.003s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	46.418s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	48.983s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	42.289s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	102.326s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	3187.780s	15416.974us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_no_meas	5746.300s	28716.714us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5856.690s	29573.007us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3135.300s	16360.633us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3035.710s	35115.451us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3035.710s	35115.451us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	157.360s	2519.847us	1	1	100.00
	chip_sw_aes_enc_jitter_en	182.950s	3021.194us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	190.370s	3120.521us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	130.550s	2395.386us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	901.590s	7947.711us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	170.600s	3116.164us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	359.810s	5449.659us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	375.100s	5999.506us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	483.570s	5685.038us	1	1	100.00
	chip_plic_all_irqs_10	289.280s	4149.360us	1	1	100.00
	chip_plic_all_irqs_20	370.550s	4504.126us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	194.690s	3603.261us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1181.650s	14326.822us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	303.490s	3732.667us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	120.250s	2962.859us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.152s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1102.500s	7803.804us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	841.360s	7075.421us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	797.830s	7624.154us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	7956.740s	256368.923us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	208.140s	3319.551us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	265.610s	6668.029us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	208.140s	3319.551us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	347.910s	7946.984us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	347.910s	7946.984us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	267.910s	6898.080us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	354.980s	5775.135us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	580.330s	5881.824us	1	1	100.00
	chip_sw_aes_idle	130.550s	2395.386us	1	1	100.00
	chip_sw_hmac_enc_idle	200.910s	2979.569us	1	1	100.00
	chip_sw_kmac_idle	112.930s	2778.255us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	306.710s	4371.158us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	307.280s	5312.299us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	295.750s	5259.057us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	291.690s	4895.864us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	750.880s	11503.488us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	400.490s	4377.076us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	329.110s	4757.685us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	400.540s	4307.685us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	377.160s	5143.267us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	430.510s	4466.454us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	382.720s	5404.978us	1	1	100.00
	chip_sw_ast_clk_outputs	754.140s	8014.143us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	557.470s	12545.696us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	400.540s	4307.685us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	377.160s	5143.267us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	409.870s	4835.007us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	585.430s	6418.618us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3919.070s	18598.029us	1	1	100.00
	chip_sw_aes_enc_jitter_en	182.950s	3021.194us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	785.190s	7944.609us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	171.410s	3133.610us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1152.790s	10114.719us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	179.550s	2799.901us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	342.760s	5298.976us	1	1	100.00
	chip_sw_clkmgr_jitter	133.820s	2458.287us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	152.140s	2595.180us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	394.330s	5387.906us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	674.890s	7462.847us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3991.920s	25854.383us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	172.170s	3135.537us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	160.510s	3727.294us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	731.830s	8221.488us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	204.190s	3506.087us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	381.510s	5960.266us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1096.960s	24322.136us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	19805.610s	229894.239us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	754.140s	8014.143us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	363.980s	4627.006us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	265.290s	3757.160us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	375.100s	5999.506us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1102.500s	7803.804us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2151.640s	24451.760us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	251.060s	4162.995us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	465.350s	6021.597us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	212.690s	2721.319us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	3378.160s	18112.500us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	130.930s	3214.053us	1	1	100.00
	chip_sw_edn_entropy_reqs	735.380s	6284.969us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	130.930s	3214.053us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2151.640s	24451.760us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	161.060s	3199.409us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1006.620s	21707.433us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	532.830s	5611.129us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	585.430s	6418.618us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	412.010s	4584.070us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	409.870s	4835.007us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3481.590s	43251.863us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1006.620s	21707.433us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	210.870s	2881.827us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	708.980s	6170.507us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	162.190s	2908.726us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3481.590s	43251.863us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	162.190s	2908.726us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	162.190s	2908.726us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	162.190s	2908.726us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	162.190s	2908.726us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	375.100s	5999.506us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	330.990s	10854.681us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	568.160s	5313.742us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	376.020s	5316.125us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	376.020s	5316.125us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	158.920s	3221.094us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	171.410s	3133.610us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	200.910s	2979.569us	1	1	100.00
chip_sw_hmac_all_configurations				0	1	0.00
	chip_sw_hmac_oneshot	1587.890s	12026.963us	0	1	0.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1645.720s	12018.543us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	346.380s	5055.434us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	377.460s	5131.348us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	433.260s	5604.265us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	359.700s	4828.407us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	708.980s	6170.507us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1152.790s	10114.719us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	713.250s	6936.440us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	901.590s	7947.711us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4120.710s	20026.610us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	178.890s	3565.261us	1	1	100.00
	chip_sw_kmac_mode_kmac	209.590s	3330.908us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	179.550s	2799.901us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	708.980s	6170.507us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	636.760s	13792.775us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	139.680s	2523.366us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1358.210s	11233.685us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	112.930s	2778.255us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	359.810s	5449.659us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	192.450s	3751.430us	1	1	100.00
	chip_tap_straps_rma	326.720s	7030.874us	1	1	100.00
	chip_tap_straps_prod	112.980s	2841.940us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	163.350s	2768.951us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	636.760s	13792.775us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	636.760s	13792.775us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	636.760s	13792.775us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1389.080s	11336.051us	1	1	100.00
chip_sw_lc_ctrl_broadcast				20	22	90.91
	chip_sw_flash_ctrl_lc_rw_en	162.190s	2908.726us	0	1	0.00
	chip_sw_flash_rma_unlocked	3481.590s	43251.863us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	186.690s	3398.750us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	556.730s	8213.339us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	631.710s	7319.870us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	434.210s	6461.542us	0	1	0.00
	chip_sw_lc_ctrl_transition	636.760s	13792.775us	1	1	100.00
	chip_sw_keymgr_key_derivation	708.980s	6170.507us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	398.090s	8823.649us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	497.930s	7600.063us	1	1	100.00
	chip_prim_tl_access	330.990s	10854.681us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	557.470s	12545.696us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	400.490s	4377.076us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	329.110s	4757.685us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	400.540s	4307.685us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	377.160s	5143.267us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	430.510s	4466.454us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	382.720s	5404.978us	1	1	100.00
	chip_tap_straps_dev	192.450s	3751.430us	1	1	100.00
	chip_tap_straps_rma	326.720s	7030.874us	1	1	100.00
	chip_tap_straps_prod	112.980s	2841.940us	1	1	100.00
	chip_rv_dm_lc_disabled	280.750s	9075.652us	1	1	100.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	192.330s	4153.959us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	76.880s	3002.319us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	88.280s	3339.759us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	150.280s	3541.921us	1	1	100.00
chip_lc_test_locked				2	2	100.00
	chip_sw_lc_walkthrough_testunlocks	1814.250s	30049.094us	1	1	100.00
	chip_rv_dm_lc_disabled	280.750s	9075.652us	1	1	100.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	685.810s	11904.957us	0	1	0.00
	chip_sw_lc_walkthrough_prod	738.160s	12330.651us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	524.650s	10015.856us	1	1	100.00
	chip_sw_lc_walkthrough_rma	423.930s	7487.375us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1814.250s	30049.094us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				1	3	33.33
	chip_sw_lc_ctrl_volatile_raw_unlock	70.660s	1750.329us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	58.690s	2458.951us	0	1	0.00
	rom_volatile_raw_unlock	78.405s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3688.640s	17677.057us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3919.070s	18598.029us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	580.330s	5881.824us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	580.330s	5881.824us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	580.330s	5881.824us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	291.260s	3934.261us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	636.760s	13792.775us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1006.620s	21707.433us	1	1	100.00
	chip_sw_otbn_mem_scramble	291.260s	3934.261us	1	1	100.00
	chip_sw_keymgr_key_derivation	708.980s	6170.507us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	330.360s	4351.140us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	137.790s	2501.129us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1006.620s	21707.433us	1	1	100.00
	chip_sw_otbn_mem_scramble	291.260s	3934.261us	1	1	100.00
	chip_sw_keymgr_key_derivation	708.980s	6170.507us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	330.360s	4351.140us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	137.790s	2501.129us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	636.760s	13792.775us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	398.450s	5358.068us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	163.350s	2768.951us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	186.690s	3398.750us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	556.730s	8213.339us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	631.710s	7319.870us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	434.210s	6461.542us	0	1	0.00
	chip_sw_lc_ctrl_transition	636.760s	13792.775us	1	1	100.00
	chip_prim_tl_access	330.990s	10854.681us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	330.990s	10854.681us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	903.130s	7428.215us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	74.120s	2646.974us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	947.210s	25500.183us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	197.660s	7722.451us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	458.770s	7392.861us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	370.880s	5951.841us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	752.530s	23936.320us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	877.790s	13319.864us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	347.910s	7946.984us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	772.520s	12018.221us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	373.690s	4555.491us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	74.120s	2646.974us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	299.660s	4570.447us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1293.670s	19760.537us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	379.860s	7944.895us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	178.030s	3777.750us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	261.310s	5538.548us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	773.270s	9285.887us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	998.310s	10149.025us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	2017.320s	28779.721us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	169.350s	3415.268us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	375.100s	5999.506us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	398.090s	8823.649us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	398.090s	8823.649us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	998.310s	10149.025us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	261.310s	5538.548us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	373.690s	4555.491us	1	1	100.00
	chip_sw_pwrmgr_smoketest	265.610s	6668.029us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	304.980s	4733.748us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	361.920s	5066.502us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	211.770s	4351.097us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1181.650s	14326.822us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	155.980s	2929.268us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	375.100s	5999.506us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	841.360s	7075.421us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	449.520s	5080.379us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	492.740s	5534.381us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	181.550s	3198.095us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	137.790s	2501.129us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	361.920s	5066.502us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	361.920s	5066.502us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1562.180s	16908.154us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	919.740s	13556.869us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	304.980s	4733.748us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	214.510s	3368.089us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	379.180s	7200.834us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	326.720s	7030.874us	1	1	100.00
chip_rv_dm_lc_disabled				1	1	100.00
	chip_rv_dm_lc_disabled	280.750s	9075.652us	1	1	100.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	483.570s	5685.038us	1	1	100.00
	chip_plic_all_irqs_10	289.280s	4149.360us	1	1	100.00
	chip_plic_all_irqs_20	370.550s	4504.126us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	203.120s	3170.216us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	163.950s	3545.980us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3167.770s	15420.294us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	363.950s	5173.352us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	211.890s	3938.539us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	177.770s	3504.330us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	186.070s	3403.296us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	330.360s	4351.140us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	342.760s	5298.976us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	541.970s	8129.637us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	325.130s	6508.835us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	497.930s	7600.063us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	375.100s	5999.506us	1	1	100.00
	chip_sw_data_integrity_escalation	392.770s	5509.255us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	773.270s	9285.887us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1094.260s	23709.588us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	154.710s	2983.668us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	237.170s	3810.657us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	341.020s	4616.785us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1094.260s	23709.588us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1094.260s	23709.588us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2587.430s	20655.485us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2587.430s	20655.485us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	346.820s	6696.783us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3035.710s	35115.451us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	192.650s	3316.713us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	142.300s	2406.713us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	289.250s	3681.990us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	315.810s	4075.430us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	1023.670s	8701.601us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	4828.710s	32175.616us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1861.690s	12500.987us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	146.210s	2553.730us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	156.490s	3043.235us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	112.330s	3225.187us	1	1	100.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9898.550s	72254.277us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1107.560s	6731.770us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	182.320s	3980.579us	0	1	0.00
	rom_e2e_jtag_debug_dev	473.890s	7944.639us	0	1	0.00
	rom_e2e_jtag_debug_rma	161.950s	3502.623us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	64.960s	2200.001us	0	1	0.00
	rom_e2e_jtag_inject_dev	74.440s	2400.480us	0	1	0.00
	rom_e2e_jtag_inject_rma	75.180s	1926.324us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	16.043s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	283.170s	3826.917us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	344.100s	3228.562us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	475.440s	3695.118us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1086.650s	8415.437us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	227.600s	2979.998us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	636.010s	5493.227us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	72.090s	2723.330us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	207.380s	3541.304us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	361.640s	5967.464us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	347.410s	6328.094us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	998.310s	10149.025us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	182.320s	3980.579us	0	1	0.00
	rom_e2e_jtag_debug_dev	473.890s	7944.639us	0	1	0.00
	rom_e2e_jtag_debug_rma	161.950s	3502.623us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	376.070s	5538.158us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	375.100s	5999.506us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5636.300s	38393.099us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5636.300s	38393.099us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	198.390s	4272.210us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	381.390s	4937.189us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3027.710s	19146.117us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	229.510s	2951.860us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	28.320s	10.200us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	4.710s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	164.390s	3001.688us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	170.710s	2762.341us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	242.620s	4049.828us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	8.015s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	233.240s	3323.899us	1	1	100.00
	ate_bootstrap_flash_erase	634.250s	10010.280us	0	1	0.00
	ate_bootstrap_one_frame	6724.760s	45830.872us	1	1	100.00
	ate_bootstrap_disjoint	9893.350s	84780.599us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	65381059913627707069363919879320026282996983296798421233033233584324422179138	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	69479727943262700501323950695223525258981085827383816084735924913859737981114	None	Waiting for it to complete... Another command (pid=347924) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	84233539209374235989658162662288018824686192191589582370339281285875599715416	None	---- STDERR ---- Another command (pid=488235) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	105047669390329547286686715026750432079763798490012800870463715348670535604210	None	---- STDERR ---- Another command (pid=488235) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=392562) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	91176508181302804090054847005602656917083049886363276835699794879890761258359	None	Another command (pid=494599) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=581067) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=584044) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	89122407077138665610113902120851317568668172593152710997813061724427721572039	None	Another command (pid=392562) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=503861) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=582097) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	19535746034106230031503567756097736508978576946435447380704249790513510167134	None	Another command (pid=595150) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=596890) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=585624) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	36678488544421740238434189694691847997945454558428054847239757070440254364963	None	---- STDERR ---- Another command (pid=488235) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=392562) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	17240426983085161272287469836659588238926129252882082190623868505833712622135	None	Another command (pid=581067) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=436375) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=584044) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	84656594901210241108068054413872866569165251363092241656130064581672890844397	None	Another command (pid=488235) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=489464) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=392562) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	44433597888764248112670121712268156910992957646911180183910517051880279781249	None	Another command (pid=473298) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=416426) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=494599) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27965874372397926301983059077527998420315159072700589645515443956363676655129	None	---- STDERR ---- Another command (pid=488235) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	53597205445352234381003814363304833211846171619692967385084041661867789279857	None	Another command (pid=586552) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=620307) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=628402) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	67521734179282748508761261877749803651419170831752022447671632815273257736658	None	Another command (pid=722156) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=733816) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=755790) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	10450679763235079001367345037928848365513638625719298384310070787812170635489	None	Another command (pid=831899) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=825723) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=764382) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	37173645755945842288600280617754939589188739678220261684690838727258378942847	None	Another command (pid=608100) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=628402) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=630082) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	39192623667307274440121962448084145776824752167547163153356700213684424941627	None	---- STDERR ---- Another command (pid=347924) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	45364299156359117433413884417952197152903995268081441639391092061926957286273	None	Another command (pid=372235) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=351349) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=393001) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	69465464797797572610573226177313974288285387896350689361362528975885905797354	None	Another command (pid=477763) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=380932) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=476586) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	21390649894726664122829454026491478677804736949181705118966599217697762843518	None	Another command (pid=448799) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=376049) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=380932) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	43811823580509691092227739889508818186660495081303170779571979634615151511623	None	Another command (pid=501538) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=582097) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=581067) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	24230225462340436536820939191712288171770800540963072341870594998849270206329	None	Another command (pid=420587) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=392938) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=360508) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	72201079969585877215251528646797743865221377013021328681179681567212137894627	None	Another command (pid=421883) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=420587) is running. Waiting for it to complete on the server (server_pid=349011)... Another command (pid=448799) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	68467302141841952926382921282776021854008348966108116370835543837022362791099	None	---- STDERR ---- Another command (pid=347924) is running. Waiting for it to complete on the server (server_pid=349011)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	86170304388878966303787887695353013150642096778716358761941603397633538790642	367	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20394487933271462109365962533221211637243878735063027225959046814946686354593	366	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	40927487898007614728439078984132399485379019904076566622112787482992970089813	368	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	33980218969229984660840012762346083941030661049322924270646006800824030688938	328	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	5380097547924668449144020966493202650644275435703052638716134061631398636714	328	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	769884992472479285599599341748863739301064222870615695466299465625548404286	326	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access				5 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	50998638066025557655171053790303876636569798731399773832872234666585493189209	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	26565839451464177677292357777989089901887965988410587532660693721439361916858	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	56400570089178686625239987587256108220404343604983555017332979765070267129148	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	85618000464951907419795544871849856033381641822334555902182645991733926530944	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	95830743086788189988928670378722550123886973333863823574118140007609197818416	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	61692771986958817753188195718407621413701679746475893288942948947649593317508	369	UVM_INFO @ 11904.956740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	2570483575746141044584598997720227636116665442460423582201484018858484837848	369	UVM_INFO @ 12330.651040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	37798429805012283369005654164323069567476200431443442005464471205811715751318	341	UVM_INFO @ 7487.375136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				3 test runs
	chip_sw_hmac_oneshot	27518158498720672476279989094882786522301133194787294231388297364191171702451	310	UVM_INFO @ 12026.962675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	84412243164053505893690921133505748633965351870349021475831427741648800531140	310	UVM_INFO @ 12018.542883 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	3946303722753973115733652236125767638533818568823193611466169891120739231526	338	UVM_INFO @ 20026.610238 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	74586618124519477533656435161739002586246959580205611744595256226795979036050	326	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	23412017711670112257285094080799723666816151905622024568616985895593243251668	327	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	68333936287361774328712981087481610751472203949310343699776000401905202015799	325	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				2 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	82375665748736807550943983103123509260003094862102020822368269022884846195240	315	UVM_ERROR @ 5538.548000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 5538.548000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	56600754034108027228025999121454008575584474951120703430953324485171474989014	319	UVM_ERROR @ 7946.983500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7946.983500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	113144810999138503902942422344895428474415442912397053947922127148871145568743	313	UVM_ERROR @ 3777.749656 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3777.749656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	104676018032132427507470611438586331155384300127391058838848261889774380471965	392	UVM_ERROR @ 19760.537320 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 19760.537320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	88776110292892319483206807653511925264486960207239688262512604928378814938067	363	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	72820218094547294072024703240572091136179323004072835421342292096535191363858	325	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	3406273813027431251469042275597348492132047975082727234120926525388513870112	366	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	113545194948400913810562652184097509426711270784505087810808074215842653109172	326	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	114274879304255783071636773409940363934397667651835697206592176427554883776892	301	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [] vs xz [z]) for MIO[*]				1 test run
	chip_sw_sleep_pin_mio_dio_val	4056544535804983826729667479777467706004430459080039263961524186233710161179	451	UVM_INFO @ 3569.400000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	57509055154349094564216023193949051394668409618007250887442181656973924153250	327	UVM_INFO @ 3938.538724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	65314191656622025118886689636845459027111519549819337933802742743373769879207	309	UVM_INFO @ 2908.726364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	107104386223197080915931044191320870837570620034894541760641608746143393723727	342	UVM_INFO @ 6461.542226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	48366472257842523464471246625409512767257023120577597227245395613392788119349	316	UVM_ERROR @ 3541.304376 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3541.304376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	20091316323655993844598144178840683617170853942648539695467749780521627562062	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:945) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration.				1 test run
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	75299533881117836710376959062888783654909232853093636651287126752944461500189	309	UVM_INFO @ 2458.950820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	108098449987461556331617281417703167545051238770034172948445871909097347781072	303	UVM_ERROR @ 2646.974171 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 2646.974171 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5274786320229036599123345078473799948169413175511348957703798543536674044123	332	UVM_INFO @ 35115.450967 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	77031279146115246586204989847582931816520397769602543806986850796406211262726	307	UVM_INFO @ 3116.163528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	45742290876136916567215881583321409279559507167916790544006179269308648396227	308	UVM_INFO @ 2962.858600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	86263897511873462161527688991830972053203031159549230054914720663405575304546	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_tl_errors	69797511698313527355089147044179311149879831858142902451149976049988623627274	217	TL item was: req: (cip_tl_seq_item@35758) { a_addr: 'h10344 a_data: 'he55dae4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h1aeee d_param: 'h0 d_source: 'h23 d_data: 'hc51513 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd5b a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2283.776124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	84479908608909394311270363934861890489228756472092468725973847456770451774742	343	UVM_INFO @ 3826.916940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_idle_load	53982795550310957590531759264204390106363930691252984597263429702120262974786	312	UVM_INFO @ 3758.620000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_sleep_load	108079828685773446554320193542178254938018326776319342292385906395956442760197	318	UVM_INFO @ 3978.155000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	83140083100455640275480738248512299434182748820400898329953421467280721701632	327	UVM_INFO @ 14465.606383 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	102805839042851100642488513983280673455525175895754070351818761812221500353132	272	UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	60326382702335292371515830003991891490120734187558606657968941548396670304106	325	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	53441973128906687827132134877161023434666607914673068787906295504487527758285	325	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [] vs [*])				1 test run
	rom_e2e_jtag_debug_test_unlocked0	35770923314478447251619270272640867246091212666729851896730827816072474821669	317	UVM_INFO @ 3980.578916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds				1 test run
	rom_e2e_jtag_debug_rma	79384519870944264851243020173610266285079235642988406826433488749964690349676	318	UVM_INFO @ 3502.623364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_meas	74479140372624978302401898829682369458126591999503425604260377711793553610778	319	UVM_INFO @ 15416.974150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	75927600256836924720029315981376535696280073261381258839143737409306524099818	327	UVM_ERROR @ 4178.851686 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4178.851686 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---