Simulation Results: clkmgr

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.65 %
  • code
  • 98.01 %
  • assert
  • 95.20 %
  • func
  • 84.73 %
  • line
  • 98.88 %
  • branch
  • 98.43 %
  • cond
  • 93.57 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.890s 80.440us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.730s 20.070us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.810s 14.798us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.490s 398.715us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.990s 54.948us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.270s 34.609us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.810s 14.798us 1 1 100.00
clkmgr_csr_aliasing 0.990s 54.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.790s 32.085us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.700s 42.974us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.700s 41.465us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.680s 17.944us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.890s 80.440us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 7.080s 1398.351us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 9.390s 2059.229us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 7.080s 1398.351us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 12.080s 4237.097us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.820s 54.078us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.300s 641.946us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.300s 641.946us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 20.070us 1 1 100.00
clkmgr_csr_rw 0.810s 14.798us 1 1 100.00
clkmgr_csr_aliasing 0.990s 54.948us 1 1 100.00
clkmgr_same_csr_outstanding 1.280s 170.410us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 20.070us 1 1 100.00
clkmgr_csr_rw 0.810s 14.798us 1 1 100.00
clkmgr_csr_aliasing 0.990s 54.948us 1 1 100.00
clkmgr_same_csr_outstanding 1.280s 170.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 30.170s 10040.603us 0 1 0.00
clkmgr_tl_intg_err 42.030s 10017.200us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.630s 136.924us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.630s 136.924us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.630s 136.924us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.630s 136.924us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 822.620s 200000.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 42.030s 10017.200us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 7.080s 1398.351us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 9.390s 2059.229us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.630s 136.924us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.680s 32.458us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.730s 25.223us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.760s 27.183us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.860s 21.437us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.790s 65.159us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.810s 14.798us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 30.170s 10040.603us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.810s 14.798us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.810s 14.798us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 30.170s 10040.603us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.830s 1532.369us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 44.890s 7604.438us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 2 test runs
clkmgr_sec_cm 44400105090959190421648885199873527207076780095830114746620932459015074849793 101
UVM_INFO @ 10040603046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 41551119776401076218617132396145332455473403192958793508520096421043441272054 101
UVM_INFO @ 10017200471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 11617289563135433929337164374624337505419980479295054883001551068417521495796 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---