Simulation Results: edn/edn0

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.02 %
  • code
  • 81.46 %
  • assert
  • 95.66 %
  • func
  • 80.95 %
  • line
  • 97.23 %
  • branch
  • 90.93 %
  • cond
  • 86.48 %
  • toggle
  • 83.20 %
  • FSM
  • 49.46 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.920s 18.629us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 54.874us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.840s 16.896us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.820s 159.451us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.340s 40.423us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.110s 41.494us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.840s 16.896us 1 1 100.00
edn_csr_aliasing 1.340s 40.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.330s 32.689us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.330s 32.689us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.330s 32.689us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.930s 29.324us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.200s 39.530us 1 1 100.00
errs 1 1 100.00
edn_err 1.090s 59.669us 1 1 100.00
disable 2 2 100.00
edn_disable 0.850s 71.687us 1 1 100.00
edn_disable_auto_req_mode 0.950s 99.180us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.010s 76.573us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.910s 23.474us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.880s 73.381us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.460s 49.244us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.460s 49.244us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 54.874us 1 1 100.00
edn_csr_rw 0.840s 16.896us 1 1 100.00
edn_csr_aliasing 1.340s 40.423us 1 1 100.00
edn_same_csr_outstanding 1.040s 79.477us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 54.874us 1 1 100.00
edn_csr_rw 0.840s 16.896us 1 1 100.00
edn_csr_aliasing 1.340s 40.423us 1 1 100.00
edn_same_csr_outstanding 1.040s 79.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.400s 1146.740us 1 1 100.00
edn_tl_intg_err 3.220s 338.307us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.070s 24.287us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.200s 39.530us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.400s 1146.740us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.400s 1146.740us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.400s 1146.740us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.400s 1146.740us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.200s 39.530us 1 1 100.00
edn_sec_cm 6.400s 1146.740us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.200s 39.530us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.220s 338.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 59.540s 13117.293us 1 1 100.00