Simulation Results: edn/edn1

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.49 %
  • code
  • 84.66 %
  • assert
  • 97.14 %
  • func
  • 80.67 %
  • line
  • 98.33 %
  • branch
  • 93.72 %
  • cond
  • 91.15 %
  • toggle
  • 95.76 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 18.520us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.760s 15.906us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.870s 38.589us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.430s 298.906us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.210s 202.429us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.080s 60.578us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.870s 38.589us 1 1 100.00
edn_csr_aliasing 1.210s 202.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.690s 72.656us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.690s 72.656us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.690s 72.656us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.960s 19.873us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.990s 48.930us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 26.930us 1 1 100.00
disable 2 2 100.00
edn_disable 0.740s 21.576us 1 1 100.00
edn_disable_auto_req_mode 1.190s 117.867us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.080s 220.606us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 13.894us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.940s 73.773us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.220s 207.996us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.220s 207.996us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.760s 15.906us 1 1 100.00
edn_csr_rw 0.870s 38.589us 1 1 100.00
edn_csr_aliasing 1.210s 202.429us 1 1 100.00
edn_same_csr_outstanding 1.350s 227.085us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.760s 15.906us 1 1 100.00
edn_csr_rw 0.870s 38.589us 1 1 100.00
edn_csr_aliasing 1.210s 202.429us 1 1 100.00
edn_same_csr_outstanding 1.350s 227.085us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.380s 1177.831us 1 1 100.00
edn_tl_intg_err 1.260s 183.309us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.900s 58.849us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.990s 48.930us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.380s 1177.831us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.380s 1177.831us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.380s 1177.831us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.380s 1177.831us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.990s 48.930us 1 1 100.00
edn_sec_cm 3.380s 1177.831us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.990s 48.930us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.260s 183.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 29.720s 8041.851us 1 1 100.00