Simulation Results: flash_ctrl

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.78 %
  • code
  • 94.29 %
  • assert
  • 97.01 %
  • func
  • 96.04 %
  • line
  • 96.06 %
  • branch
  • 97.19 %
  • cond
  • 93.75 %
  • toggle
  • 98.08 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 52.100s 249.241us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 12.610s 51.860us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 14.020s 31.076us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.040s 71.217us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 42.190s 1318.583us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 23.880s 824.364us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.930s 72.464us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.040s 71.217us 1 1 100.00
flash_ctrl_csr_aliasing 23.880s 824.364us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.110s 22.993us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.200s 19.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 12.420s 406.481us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 32.950s 60.375us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1188.160s 340458.615us 1 1 100.00
flash_ctrl_hw_rma_reset 569.140s 160200.340us 1 1 100.00
flash_ctrl_lcmgr_intg 7.410s 102.892us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1052.180s 291148.484us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 200.290s 20461.769us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 7.250s 44.372us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2948.290s 287602.746us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 48.040s 773.259us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 12.990s 30.953us 1 1 100.00
flash_ctrl_rw_evict_all_en 15.520s 33.717us 1 1 100.00
flash_ctrl_re_evict 17.600s 96.448us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 148.000s 2001.405us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 148.000s 2001.405us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 163.510s 10391.328us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.020s 104.676us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 178.770s 205.767us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 326.350s 22140.776us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 352.920s 2567.367us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 829.040s 501.456us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.360s 138.287us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 123.480s 6386.225us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 11.850s 43.927us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.740s 27.082us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 437.930s 12999.590us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 153.580s 10041.959us 1 1 100.00
flash_ctrl_otp_reset 45.830s 621.700us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1188.160s 340458.615us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 196.940s 7301.645us 1 1 100.00
flash_ctrl_intr_wr 59.590s 14308.759us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 163.220s 17631.258us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 115.760s 62896.299us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 39.790s 2268.571us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 40.900s 2646.247us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 13.070s 26.517us 1 1 100.00
flash_ctrl_ro_derr 102.430s 4007.365us 1 1 100.00
flash_ctrl_rw_derr 164.850s 6365.004us 1 1 100.00
flash_ctrl_derr_detect 100.150s 802.956us 1 1 100.00
flash_ctrl_integrity 478.400s 19182.683us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.860s 46.482us 1 1 100.00
flash_ctrl_ro_serr 84.070s 688.492us 1 1 100.00
flash_ctrl_rw_serr 124.020s 1691.328us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 41.140s 718.802us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 61.320s 1110.841us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 134.320s 5237.378us 1 1 100.00
flash_ctrl_write_word_sweep 7.330s 43.501us 1 1 100.00
flash_ctrl_read_word_sweep 8.920s 48.248us 1 1 100.00
flash_ctrl_ro 56.690s 514.462us 1 1 100.00
flash_ctrl_rw 415.790s 10879.266us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.370s 571.486us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 576.480s 83766.733us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 55.170s 10035.444us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.350s 187.116us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.410s 17.091us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 11.670s 126.253us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 11.670s 126.253us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.020s 31.076us 1 1 100.00
flash_ctrl_csr_rw 9.040s 71.217us 1 1 100.00
flash_ctrl_csr_aliasing 23.880s 824.364us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.070s 79.654us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.020s 31.076us 1 1 100.00
flash_ctrl_csr_rw 9.040s 71.217us 1 1 100.00
flash_ctrl_csr_aliasing 23.880s 824.364us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.070s 79.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 41.660s 310.359us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 41.660s 310.359us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 41.660s 310.359us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 41.660s 310.359us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 23.220s 333.654us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1841.450s 2767.547us 1 1 100.00
flash_ctrl_tl_intg_err 207.570s 1613.812us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 207.570s 1613.812us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 207.570s 1613.812us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 17.780s 261.779us 1 1 100.00
flash_ctrl_wr_intg 6.750s 54.347us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 52.100s 249.241us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 45.830s 621.700us 1 1 100.00
flash_ctrl_disable 11.850s 43.927us 1 1 100.00
flash_ctrl_sec_info_access 41.360s 2230.081us 1 1 100.00
flash_ctrl_connect 7.740s 27.082us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.550s 22.908us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.040s 71.217us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 41.660s 310.359us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.040s 71.217us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 41.660s 310.359us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.040s 71.217us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 41.660s 310.359us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 11.850s 43.927us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 17.780s 261.779us 1 1 100.00
flash_ctrl_access_after_disable 6.970s 20.588us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 16.240s 52.164us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 11.850s 43.927us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.020s 104.676us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 415.790s 10879.266us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 124.020s 1691.328us 1 1 100.00
flash_ctrl_rw_derr 164.850s 6365.004us 1 1 100.00
flash_ctrl_integrity 478.400s 19182.683us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1188.160s 340458.615us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1841.450s 2767.547us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1841.450s 2767.547us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1841.450s 2767.547us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1841.450s 2767.547us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.730s 810.537us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.060s 95.782us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 9.820s 30.767us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1841.450s 2767.547us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1841.450s 2767.547us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1841.450s 2767.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 23.480s 76.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 139.400s 737.761us 1 1 100.00