Simulation Results: hmac

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.09 %
  • code
  • 98.40 %
  • assert
  • 98.02 %
  • func
  • 43.85 %
  • line
  • 99.74 %
  • branch
  • 99.17 %
  • cond
  • 96.01 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.170s 786.759us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.900s 18.753us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 56.140us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.390s 1034.799us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.680s 194.750us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.730s 39.809us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 56.140us 1 1 100.00
hmac_csr_aliasing 2.680s 194.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 46.320s 9846.949us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 26.680s 2662.570us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 190.830s 6823.760us 1 1 100.00
hmac_test_sha384_vectors 20.450s 1203.800us 1 1 100.00
hmac_test_sha512_vectors 441.710s 61051.288us 1 1 100.00
hmac_test_hmac256_vectors 6.340s 844.600us 1 1 100.00
hmac_test_hmac384_vectors 7.750s 1816.041us 1 1 100.00
hmac_test_hmac512_vectors 6.680s 808.296us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.620s 5156.629us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 439.520s 3323.119us 1 1 100.00
error 1 1 100.00
hmac_error 37.680s 945.660us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 115.720s 23899.570us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.170s 786.759us 1 1 100.00
hmac_long_msg 46.320s 9846.949us 1 1 100.00
hmac_back_pressure 26.680s 2662.570us 1 1 100.00
hmac_datapath_stress 439.520s 3323.119us 1 1 100.00
hmac_burst_wr 12.620s 5156.629us 1 1 100.00
hmac_stress_all 267.910s 107172.749us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.170s 786.759us 1 1 100.00
hmac_long_msg 46.320s 9846.949us 1 1 100.00
hmac_back_pressure 26.680s 2662.570us 1 1 100.00
hmac_datapath_stress 439.520s 3323.119us 1 1 100.00
hmac_wipe_secret 115.720s 23899.570us 1 1 100.00
hmac_test_sha256_vectors 190.830s 6823.760us 1 1 100.00
hmac_test_sha384_vectors 20.450s 1203.800us 1 1 100.00
hmac_test_sha512_vectors 441.710s 61051.288us 1 1 100.00
hmac_test_hmac256_vectors 6.340s 844.600us 1 1 100.00
hmac_test_hmac384_vectors 7.750s 1816.041us 1 1 100.00
hmac_test_hmac512_vectors 6.680s 808.296us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.170s 786.759us 1 1 100.00
hmac_long_msg 46.320s 9846.949us 1 1 100.00
hmac_back_pressure 26.680s 2662.570us 1 1 100.00
hmac_datapath_stress 439.520s 3323.119us 1 1 100.00
hmac_burst_wr 12.620s 5156.629us 1 1 100.00
hmac_error 37.680s 945.660us 1 1 100.00
hmac_wipe_secret 115.720s 23899.570us 1 1 100.00
hmac_test_sha256_vectors 190.830s 6823.760us 1 1 100.00
hmac_test_sha384_vectors 20.450s 1203.800us 1 1 100.00
hmac_test_sha512_vectors 441.710s 61051.288us 1 1 100.00
hmac_test_hmac256_vectors 6.340s 844.600us 1 1 100.00
hmac_test_hmac384_vectors 7.750s 1816.041us 1 1 100.00
hmac_test_hmac512_vectors 6.680s 808.296us 1 1 100.00
hmac_stress_all 267.910s 107172.749us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 267.910s 107172.749us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.650s 99.625us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.780s 47.561us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.390s 242.200us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.390s 242.200us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.900s 18.753us 1 1 100.00
hmac_csr_rw 1.000s 56.140us 1 1 100.00
hmac_csr_aliasing 2.680s 194.750us 1 1 100.00
hmac_same_csr_outstanding 0.960s 217.566us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.900s 18.753us 1 1 100.00
hmac_csr_rw 1.000s 56.140us 1 1 100.00
hmac_csr_aliasing 2.680s 194.750us 1 1 100.00
hmac_same_csr_outstanding 0.960s 217.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.890s 315.848us 1 1 100.00
hmac_tl_intg_err 2.000s 435.941us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 435.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.170s 786.759us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.650s 192.143us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 265.530s 6555.899us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.870s 97.467us 1 1 100.00