Simulation Results: lc_ctrl/volatile_unlock_disabled

 
04/06/2026 15:30:32 DVSim: v1.49.9 sha: 53fb331 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.45 %
  • code
  • 84.04 %
  • assert
  • 94.97 %
  • func
  • 92.35 %
  • line
  • 96.57 %
  • branch
  • 93.85 %
  • cond
  • 79.29 %
  • toggle
  • 87.86 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.250s 16.287us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.960s 30.956us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.940s 52.843us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.230s 53.949us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 33.182us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.220s 28.709us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.940s 52.843us 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 33.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.440s 278.482us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.660s 695.880us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.340s 13.226us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.030s 193.394us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.990s 372.111us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.980s 6288.977us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.990s 372.111us 1 1 100.00
lc_ctrl_prog_failure 2.030s 193.394us 1 1 100.00
lc_ctrl_errors 8.980s 6288.977us 1 1 100.00
lc_ctrl_security_escalation 3.500s 180.018us 1 1 100.00
lc_ctrl_jtag_state_failure 33.170s 1459.939us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.900s 177.161us 1 1 100.00
lc_ctrl_jtag_errors 20.600s 4075.708us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.660s 175.717us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.630s 1784.983us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.900s 177.161us 1 1 100.00
lc_ctrl_jtag_errors 20.600s 4075.708us 1 1 100.00
lc_ctrl_jtag_access 2.600s 106.524us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.930s 1358.685us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.210s 329.254us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.240s 119.363us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.610s 676.841us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.070s 425.966us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.560s 31.533us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.230s 51.863us 1 1 100.00
lc_ctrl_jtag_alert_test 1.800s 467.576us 1 1 100.00
jtag_priority 0 1 0.00
lc_ctrl_jtag_priority 14.440s 25418.224us 0 1 0.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 40.618us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 235.000s 12963.092us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.100s 39.949us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.040s 101.441us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.040s 101.441us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 30.956us 1 1 100.00
lc_ctrl_csr_rw 0.940s 52.843us 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 33.182us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.030s 22.843us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 30.956us 1 1 100.00
lc_ctrl_csr_rw 0.940s 52.843us 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 33.182us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.030s 22.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.170s 286.303us 1 1 100.00
lc_ctrl_tl_intg_err 1.500s 72.326us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.500s 72.326us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.660s 695.880us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.990s 372.111us 1 1 100.00
lc_ctrl_sec_cm 8.170s 286.303us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.990s 372.111us 1 1 100.00
lc_ctrl_sec_cm 8.170s 286.303us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.990s 372.111us 1 1 100.00
lc_ctrl_sec_cm 8.170s 286.303us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.990s 372.111us 1 1 100.00
lc_ctrl_sec_cm 8.170s 286.303us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.990s 372.111us 1 1 100.00
lc_ctrl_sec_cm 8.170s 286.303us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.990s 372.111us 1 1 100.00
lc_ctrl_sec_cm 8.170s 286.303us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.990s 372.111us 1 1 100.00
lc_ctrl_sec_cm 8.170s 286.303us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.990s 372.111us 1 1 100.00
lc_ctrl_sec_cm 8.170s 286.303us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.500s 180.018us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.440s 278.482us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.630s 1784.983us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.360s 302.454us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.360s 302.454us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.150s 1606.128us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.260s 440.290us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.260s 440.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 43.890s 4400.141us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:135) [lc_ctrl_jtag_priority_vseq] wait for simultaneous mutex claim 1 test run
lc_ctrl_jtag_priority 21262137971793894827411738746028249330190577830339096807894283173507670617445 148
UVM_INFO @ 25418224236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---